Method of forming polycide gate

Details Method of forming polycide gate Method of forming polycide gate

1998-11-04

2000-09-19

Nguyen, Tuan H.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438595, 438303, 438655, 438683, H01L 214763

Patent

active

061211257

ABSTRACT:
A method of forming a polycide gate is provided. On a substrate having a gate oxide layer thereon, a polysilicon layer and a silicide layer are formed. A multi-insulation layer and a hard material layer are formed on the silicide layer. The multi-insulation layer comprises multiple insulation layers. The thermal expansion coefficients of these insulation layers are between the thermal expansion coefficients of the silicide layer and the hard material layer, and moreover, are closer to it of the hard material layer gradually layer by layer. The hard mask layer, multi-insulation layer, silicide layer and the polysilicon layer are then defined to form a polycide gate. A spacer is formed to cover a side wall of the gate.

REFERENCES:
patent: 5600165 (1997-02-01), Tsukamoto et al.
patent: 5679591 (1997-10-01), Lin et al.
patent: 5851927 (1998-12-01), Cox et al.
patent: 5924000 (1999-07-01), Linliu

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