Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-11-16
2002-06-25
Booth, Richard (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S316000, C438S594000, C438S266000
Reexamination Certificate
active
06410957
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to split-gate memory cells used in flash EEPROMs (Electrically Erasable Programmable Read Only Memories), and in particular, to a method of forming a poly tip to improve erasing and programming speed of the memory cell.
(2) Description of the Related Art
Erasing and programming speed of a split gate flash memory cell is governed by the capacitive coupling between different parts of the cell. As it will be described more fully later, the programming and erasing of the cell is accomplished by transferring charges between polysilicon or poly parts comprising the floating gate, control gate and the source region in the device substrate. A faster erase speed is achieved if the coupling ratio between the control gate and the floating gate is low, which in turn, is attained by having a thinner floating gate as well as a sharper edge on the gate. With conventional methods of forming split gate cells, it is difficult to have low coupling ratio because of the relatively tall sidewalls of the floating gate. This is compensated to a large extent by forming a sharp edge or tip on the floating gate. On the other hand, higher programming speed is achieved if the coupling ratio between the floating gate and the source region is higher with relatively thicker gate. It is disclosed in the embodiments of the present invention a method of forming a split gate flash memory cell having a thin floating gate and a sharp poly tip in order to improve erasing and programming speed of the cell. The method involves the use of a chemical vapor deposited CVD-top oxide other than the poly oxide that is conventionally employed in forming the floating gate, and also using to advantage a so-called “smiling effect” which is normally taught away.
Conventionally, the floating gate of a split gate memory cell is formed by growing polysilicon oxide, or, polyoxide, on the polysilicon layer that eventually becomes the floating gate while the overlying polyoxide is used as a hard mask to etch the polysilicon gate. However, depending upon the doping, grain size and the oxidation speed of the polysilicon, there is formed around the edges of the polyoxide a protrusion of a particular shape, usually variations on the well known gate bird's beak, into the polysilicon which affects the erase speed of the cell and hence the performance of the memory device. A different technique of forming the oxide over the polysilicon gate is proposed in this invention so that the protrusion in the form of a well defined and sharp poly tip can predictably be formed each time in order to provide a reliable memory cell. The sharpness of the tip improves the erase speed.
The shape and size of different portions of memory cells have different effects on the performance of the memory cells in different ways. Thus, with the well-known one-transistor memory cell, which contains one transistor and one capacitor, many variations of this simple cell have been advanced for the purposes of shrinking the size of the cell and, at the same time, improve its performance. The variations consist of different methods of forming capacitors, with single, double or triple layers of polysilicon, and different materials for the word and bit lines. Another variation which is disclosed in this invention relates to the shape of the edge of the floating gate which significantly affects the erase speed of split-gate flash memory cells.
Memory devices include electrically erasable and electrically programmable read-only memories (EEPROMs) of flash electrically erasable and electrically programmable read-only memories (flash EEPROMS). Many types of memory cells for EEPROMs or flash EEPROMs may have source and drains regions that are aligned to a floating gate or aligned to spacers. When the source and drain regions are aligned to the floating gate, a gate electrode for a select transistor is separate from the control gate electrode of the floating gate transistor. Separate select and control gates increase the size of the memory cell. If the source and drain regions are aligned to a spacer formed after the floating gate is formed, the floating gate typically does not overlie portions of the source and drain regions. Programming and erasing performance is degraded by the offset between the floating gate and source and drain regions.
Most conventional flash-EEPROM cells use a double-polysilicon (poly) structure of which the well known split-gate cell is shown in
FIG. 1
g.
The forming of the cell is shown in
FIGS. 1
a
-
1
f
which will be described shortly. In the final form of the cell shown in
FIG. 1
g,
a MOS transistor is formed on a semiconductor substrate (
10
) having a first doped region (
11
), a second doped region (
13
), a channel region (
15
), a gate oxide (
30
), a floating gate (
40
), intergate dielectric layer (
50
) and control gate (
60
). Substrate (
10
) and channel region (
15
) have a first conductivity type, and the first (
11
) and second (
13
) doped regions have a second conductivity type that is opposite the first conductivity type.
As seen in
FIG. 1
g,
the first doped region, (
11
), lies within the substrate. The second doped region, (
13
), lies within substrate (
10
) and is spaced apart form the first doped region (
11
). Channel region (
15
) lies within substrate (
10
) and between first (
11
) and second (
13
) doped regions. Gate oxide layer (
30
) overlies substrate (
10
). Floating gate (
40
), to which there is no direct electrical connection, and which overlies substrate (
10
), is separated from substrate (
10
) by a thin layer of gate oxide (
30
) while control gate (
60
), to which there is direct electrical connection, is generally positioned over the floating gate with intergate oxide (
50
) therebetween.
In the structure shown in
FIG. 1
g,
control gate (
60
) overlaps the channel region, (
17
), adjacent to channel (
15
) under the floating gate, (
40
). This structure is needed because when the cell is erased, it leaves a positive charge on the floating gate. As a result, the channel under the floating gate becomes inverted. The series MOS transistor (formed by the control gate over the channel region) is needed in order to prevent current flow from control gate to floating gate. The length of the transistor, that is the overlap of the control gate over the channel region (
17
) determines the cell performance. Furthermore, the shape of the edge (
43
) and, in particular, that of edge (
47
) can affect the programming of the cell. It is disclosed in this invention that the shape and size of edge (
47
) will affect the programming erase speed of the cell substantially. The relatively rounded shape that is found in conventional cells shown in
FIG. 1
g
and which affects the erase speed adversely is the result of the commonly used process which is illustrated in
FIGS. 1
a
-
1
e.
The same conventional process depicted in
FIGS. 1
a
-
1
f
also lends to the “smiling effect” shown in
FIG. 1
h,
which also degrades the programmability of the memory cell. Floating gate (
40
), including the overlying polyoxide layer (
45
), and the “smiling” structure are shown in
FIG. 1
h.
“Smiling” effect refers to the thickening of the edges (
35
), or “lips” of the gate oxide underlying the polysilicon floating gate of a memory cell caused—as will be apparent to those skilled in the art—by the diffusion of oxygen (
70
) during the forming of the polyoxide (
45
) over the gate as shown in
FIG. 1
h.
That is, during oxidation, oxygen (
70
) diffuses into the gate (
40
) as well as into gate oxide (
30
) through its edges (
35
) and grows the edges as shown in
FIG. 1
h.
Hence the thickness (b) at edge (
35
) becomes larger than its original thickness (a), thereby resulting in a structure having a “smiling” effect.
Now referring to a conventional method of forming a split gate flash memory cell, a layer of gate oxide (
30
) is thermally grown over substrate (
10
) as shown in
FIG. 1
a.
Next, a first polysilicon layer (
40
) is formed followed
Hsieh Chia-Ta
Kuo Di-Son
Lin Yai-Fen
Sung Hung-Cheng
Booth Richard
OKtay SeVgin
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