Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1995-06-07
1997-10-28
Jackson, Jerome
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257413, 257 51, 257395, 257752, H01L 2994, H01L 2904
Patent
active
056820550
ABSTRACT:
A method is provided for forming an improved planar structure of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A field oxide is grown across the integrated circuit patterned and etched to form an opening with substantially vertical sidewalls exposing a portion of an upper surface of a substrate underlying the field oxide where an active area will be formed. A gate electrode comprising a polysilicon gate electrode and a gate oxide are formed over the exposed portion of the substrate. The polysilicon gate has a height at its upper surface above the substrate at or above the height of the upper surface of the field oxide. The gate electrode preferably also comprises a silicide above the polysilicon and an oxide capping layer above the silicide. LDD regions are formed in the substrate adjacent the gate electrode and sidewall spacers are formed along the sides of the gate electrode including the silicide and the capping layer.
REFERENCES:
patent: 4450620 (1984-05-01), Fuls et al.
patent: 4775644 (1988-10-01), Szeto
patent: 4807013 (1989-02-01), Manocha
patent: 4841347 (1989-06-01), Hsu
patent: 4859620 (1989-08-01), Wei et al.
patent: 4868138 (1989-09-01), Chan et al.
patent: 4937643 (1990-06-01), Deslauriers et al.
patent: 5158903 (1992-10-01), Hori et al.
patent: 5192992 (1993-03-01), Kim et al.
patent: 5241193 (1993-08-01), Pfiester et al.
patent: 5319232 (1994-06-01), Pfiester
patent: 5341016 (1994-08-01), Prall et al.
patent: 5365081 (1994-11-01), Yamazaki et al.
Queirolo, et al., "Dopant Activation Carrier Mobility, and TEM Studies in Polycrystalline Silicon Films", J. Electrochem. So., V. 137, No. 3, Mar., 1990, pp. 967-970.
C.S. Pai, et al., "Chemical IVapor Deposition of Selective Epitaxial Silicon Layers", J. Electrochem. Soc., V. 137, No. 3, Mar., 1990, pp. 971-976.
Chan Tsiu C.
Huang Kuei-Wu
Smith Gregory C.
Galanthay Theodore E.
Gray John
Hill Kenneth C.
Jackson Jerome
Jorgenson Lisa K.
LandOfFree
Method of forming planarized structures in an integrated circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming planarized structures in an integrated circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming planarized structures in an integrated circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1028090