Method of forming planar isolation in integrated circuits

Details Method of forming planar isolation in integrated circuits Method of forming planar isolation in integrated circuits

1996-05-17

1998-04-07

Fourson, George R.

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Recessed oxide by localized oxidation

438697, H01L 2176

Patent

active

057364516

ABSTRACT:
A method for producing an isolation region on a surface of a semiconductor substrate includes: forming and patterning a masking layer; forming an isolating layer so that a notch exists between an edge of the masking layer and the upper surface of the isolating layer; forming a filling layer over the masking layer and the isolating layer, so that it completely fills the notch; forming field protection spacers adjacent to the masking layer; partially removing the filling layer to expose the upper surface of the isolation layer, the notch remaining filled with a part of the filling layer; and selectively etching the isolating layer from its upper limit until this upper limit is substantially coplanar with the upper surface of the semiconductor substrate. A transistor may be produced in a semiconductor substrate, having a minimum gate length, a minimum width isolation region and wide field isolation region. The isolation regions have substantially coplanar surfaces, also coplanar with an upper surface of the semiconductor substrate. The wide field isolation region has, in an upper surface, a hollow located a distance p from an interface with the upper surface of the semiconductor substrate and the minimum width isolation region has a width less than the sum of the gate length and 2p.

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1987 Symposium on VLSI Technology Digest of Technical Papers May 18-21, 1987, New York, pp. 19-20 P.A. Van Der Plas, et al. "Field Isolation Process for Submicron CMOS".
Extended Abstracts of the 1993 International Conference on Solid State Devices and Materials 29-08/1-09 1993, 1993 Tokyo JA, pp. 892-894, W.S. Yang, et al. "Bird's Beak Controlled Poly Buffered Locos Isolation (BPBL) Technology for 256MB DRAM".
Solid State Technology, vol. 37, No. 11, Nov. 1994 Washington, US, pp. 67-72, S.S. Kim, et al. "High Pressure and High Temperature Furnace Oxidation For Advances Poly-Buffered Locos".

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