Method of forming ONO flash memory devices using rapid...

Details Method of forming ONO flash memory devices using rapid... Method of forming ONO flash memory devices using rapid...

2000-08-25

2002-05-28

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Making oxide-nitride-oxide device

C438S306000

Reexamination Certificate

active

06395654

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to flash memory devices and more particularly to a method of fabricating flash memory devices having an ONO layer which contains a silicon nitride layer sandwiched between two silicon oxide layers.
2. Description of the Related Art
A flash memory having an ONO layer is illustrated in FIG.
1
. It includes an ONO layer
60
disposed on top of a silicon substrate
10
, and a control gate
71
, typically of polysilicon, disposed on top of the ONO layer
60
. The ONO layer
60
comprises a lower layer
61
made of silicon oxide, a middle layer
62
made of silicon nitride, and an upper layer
63
made of silicon oxide.
FIGS. 2A-2J
illustrate the conventional process for fabricating a flash memory device having an ONO layer. First, a silicon oxide layer
20
is thermally grown on the silicon substrate
10
to form the structure of FIG.
2
A. Then, as shown in
FIG. 2B
, nitrogen atoms (N or N
2
) are implanted into the silicon oxide layer
20
.
The nitrogen implanting step is followed by heating to anneal out the implant damage and to diffuse the implanted nitrogen to the Si/SiO
2
interface
21
and cause SiN bonds to be formed at the Si/SiO
2
interface
21
. The heating is performed in a furnace and the entire heating process takes several hours because the process requires a long time to ramp up and ramp down.
Subsequently, a silicon nitride layer
30
is deposited on top of the silicon oxide layer
20
by chemical vapor deposition (CVD).
FIG. 2C
shows the silicon nitride layer
30
deposited on tip of the silicon oxide layer
20
. A second layer of silicon oxide
40
is then formed on top of the silicon nitride layer
30
and the resulting structure is shown in FIG.
2
D. Thereafter, as shown in
FIG. 2E
, a photoresist
50
is formed on top of the
4
second silicon oxide layer
40
, and this semiconductor structure is etched until an upper surface of the silicon substrate
10
is exposed. The resulting structure, shown in
FIG. 2F
, is subsequently implanted with arsenic and boron ions using the remaining photoresist
50
as a mask and heated to diffuse the implanted ions to form source/drain regions
62
and
64
.
The remaining photoresist
50
is stripped away and, as shown in
FIG. 2G
, a polysilicon layer
70
is deposited on top of the exposed surface of the silicon substrate
10
and on top and sidewalls of the ONO layer
60
. The polysilicon layer
70
is then patterned using conventional lithography techniques and a control gate
71
remains on top of the ONO layer
60
.
FIG. 2H
shows the resulting gate structure
75
including the control gate
71
and the ONO layer
60
.
Oxide spacers
81
,
82
, shown in
FIG. 2J
, are formed on the sidewalls of the gate structure
75
by (i) depositing a conformal layer of silicon oxide
80
by CVD on the exposed surface of the silicon substrate
10
and on top and sidewalls of the gate structure
75
(FIG.
2
I), and (ii) anisotropically etching the deposited silicon oxide.
SUMMARY OF THE INVENTION
The invention provides a process for forming an ONO flash memory device using rapid thermal annealing or reoxidation that improves processing speed, reduces thermal budget, and reduces diffusion of dopants in channels.
The invention produces a gate structure for an ONO flash memory device that includes a first layer of silicon oxide on top of a semiconductor substrate, a second layer of silicon oxide, a layer of silicon nitride sandwiched between the two silicon oxide layers, and a control gate on top of the second layer of silicon oxide. Nitrogen is implanted into the first layer of silicon oxide and the semiconductor structure is heated in a rapid thermal annealing chamber to anneal out the implant damage and to diffuse the implanted nitrogen to the substrate and silicon oxide interface to cause SiN bonds to be formed at that interface. The SiN bonds is desirable because they improve the bonding strength at the interface and the nitrogen remaining in the silicon oxide layer increases the oxide bulk reliability.
The invention employs rapid thermal annealing or rapid thermal re-oxidation using a rapid thermal tool in place of heating in a conventional furnace because (i) it anneals out damage in the substrate resulting from nitrogen implantation better than the conventional furnace process and (ii) it prevents excess movement of dopants implanted in channels.
Additional objects, features and advantages of the invention will be set forth in the description of preferred embodiments which follows.


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patent: 5464792 (1995-11-01), Tseng et al.
patent: 5882987 (1999-03-01), Srikrishnan
patent: 6044203 (2000-03-01), Dawson et al.
patent: 6159795 (2000-12-01), Higashitani et al.
patent: 6184110 (2001-02-01), Ono et al.
patent: 6248628 (2001-06-01), Halliyal et al.
patent: 6248633 (2001-06-01), Ogura et al.
“ELectrical and Physical Properties of Ultrathin Reoxidized Nitrided Oxides Prepared by Rapid Thermal Processing.” Hori, T.; Iwasaki, H.; Tsuji, K. IEEE Transactions on Electron Devices, vol. 36, No. 2, 1989, pp. 340-350.*
“Evaluation of Rapid Thermal Nitrided ONO Interpoly Dielectric Resistance to Plasma Process-Induced Damage.” Cha, C.; Chor, E.; Gong, H.; Zhang, A.; Dong, Z.; and Chan, L. 4th Int'l Symposium on Plasma Process-Induced Damage, May 10-11, 1999, pp. 49-52.*
Silicon Processing for the VLSI Era. Wolf, S. and Tauber, R.N. vol. 1, second ed. Lattice Press, 2000.

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