Method of forming nonvolatile memory device

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation

Reexamination Certificate

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Details

C438S128000, C438S257000, C438S589000, C257SE21179, C257SE21532, C257SE21662

Reexamination Certificate

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08058160

ABSTRACT:
A method of forming the gate patterns of a nonvolatile memory device comprises stacking a gate insulating layer and a first conductive layer over a semiconductor substrate; forming isolation hard mask patterns over the first conductive layer; etching the first conductive layer using the isolation hard mask patterns as etch barriers, thus exposing the gate insulating layer; etching the gate insulating layer using the isolation hard mask patterns as etch barriers, thus exposing the semiconductor substrate; after exposing the semiconductor substrate, forming a passivation layer on the sidewalls of the first conductive layers and on the sidewalls of the gate insulating layers; and etching the semiconductor substrate using the passivation layer and the isolation hard mask patterns as etch barriers, thus forming trenches in the semiconductor substrate.

REFERENCES:
patent: 6171939 (2001-01-01), Lin
patent: 6228712 (2001-05-01), Kawai et al.
patent: 2007/0099380 (2007-05-01), Kim
patent: 10-2006-0000793 (2006-01-01), None
patent: 1020060029382 (2006-04-01), None
patent: 10-2008-0022398 (2008-03-01), None
patent: 10-2008-0061518 (2008-07-01), None
patent: 1020080064306 (2008-07-01), None
patent: 1020090000399 (2009-01-01), None

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