Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
1999-02-08
2001-02-20
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S704000, C438S706000, C438S710000
Reexamination Certificate
active
06191042
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87120802, filed Dec. 15, 1998.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a method of fabricating a node contact in a dynamic random access memory (DRAM).
2. Description of the Related Art
As the number of semiconductor devices incorporated in integrated circuits increases, the size of the devices needs to be decreased according to a design rule. In a photolithographic step it is necessary to avoid misalignment. That is, a node contact must be aligned with a source/drain region in a substrate. As the size of a node contact increases, alignment accuracy decreases. Thus, in practice, a node contact easily makes contact with the neighboring bit lines, which causes a short in the devices.
The conventional methods to decrease the size of a node contact include a photoresist reflow method and a polysilicon spacer method.
FIGS. 1A
to
1
C are schematic. cross-sectional views showing a photoresist reflow method for forming a node contact opening.
In
FIG. 1A
, a substrate
100
having a dielectric layer
102
. a bit line
106
, and a dielectric layer
104
formed thereon is provided. A photoresist layer
108
is formed on the dielectric layer
104
to expose a portion of the dielectric layer
104
.
In
FIG. 1B
, a thermal reflow step is performed. The increasing temperature leads to the increasing fluidity of the photoresist layer
108
. A photoresist layer
108
a
with an opening
110
a
thus is formed. The opening
110
a
is smaller than the opening
110
.
In
FIG. 1C
, the plhotoresist layer
108
a
is used as a mask. An etching step is performed. A node contact opening
112
is formed in the dielectric layers
102
and
104
to expose the substrate
100
.
However, performing the photoresist reflow method requires specific machinery, so the method cannot be easily performed.
FIGS. 2A
to
2
B are schematic, cross-sectional views showing a polysilicon spacer method for forming a node contact opening.
In
FIG. 2A
, a substrate
200
having a dielectric layer
202
, a dielectric layer
204
, and a bit line
206
formed thereon is provided. A polysilicon layer
210
having an opening
224
is formed on the dielectric layer
204
. The opening
224
in the dielectric layer
204
exposes a portion of the dielectric layer
204
. A polysilicon layer
212
, which is conformal to the opening,
224
, is formed on the polysilicon layer
210
.
FIG. 2B
, an etching step is performed. A portion of the polysilicon layer
212
is removed to form a spacer
212
a
on a sidewall of the opening
224
. The polysilicon layer
210
and the spacer
212
a
are used as masks. An etching step is performed to form a node contact opening
220
in the dielectric layer
204
and
202
until the substrate
200
is exposed.
In the above procedures for forming a node contact opening
220
, the size of the contact node opening
220
can be further decreased with the spacer
212
a
used as a mask. However, the method needs multiple, or more than two, polysilicon layers, such as polysilicon layers
210
and
212
and redundant, also more than two, etching steps, which increase the fabrication costs.
SUMMARY OF THE INVENTION
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of forming a node contact opening. A dielectric layer is formed on a substrate. An opening is formed with C
4
F
8
/Ar/CH
2
F
2
used as an etchant. A portion of the dielectric layer under the opening is etched with CHF
3
/CO used as an etchant until the substrate is exposed. A node contact opening is formed.
The invention provides a simplified and less expensive method of fabricating a node contact opening.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5369048 (1994-11-01), Hsue
patent: 5547893 (1996-08-01), Sung
patent: 5652165 (1997-07-01), Lu et al.
patent: 5710460 (1998-01-01), Leidy et al.
patent: 5728618 (1998-03-01), Tseng
patent: 5763286 (1998-06-01), Figura et al.
patent: 5843820 (1998-12-01), Lu
patent: 5915177 (1999-06-01), Tseng
Lin Kuo-Chi
Tsai Chien-Hua
Huang Jiawei
J C Patents
Perez-Ramos Vanessa
United Microelectronics Corp.
Utech Benjamin L.
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