Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1997-06-30
2001-10-09
Everhart, Caridad (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S700000, C438S637000
Reexamination Certificate
active
06300235
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to semiconductor devices and more particularly, to improved methods of forming multi-level coplanar metal/insulator films using dual damascene with sacrificial flowable oxide.
Semiconductor manufacturers must continually improve the power and performance of semiconductor devices while keeping the device size to a minimum. In an effort to maintain a small device size, most semiconductor manufacturers reduce individual components of the device to minimal dimensions. Further, manufacturers are vertically integrating more and more of these components, as opposed to using only horizontal integration to reduce the device area consumed by the components. Vertical integration is typically achieved by using several conductive layers in the device and interconnecting these layers using, for example, inter-level contacts known in the art as vias or via interconnects.
As individual component dimensions become smaller, it becomes more difficult to interconnect the various conductive layers. A recent approach to solving the problem of interconnecting the various conductive layers involves etch and mask sequences generally known in the art as damascene techniques. The damascene technique involves forming a plurality of trenches in a layer of insulator and subsequently filling them with metal which is then polished down to the surface of the insulator to form the desired metal pattern. In a process generally known as dual damascene, both the metal trenches as described above and the via interconnects electrically connecting the aforementioned metal pattern and various other conductive layers are typically filled substantially simultaneously. In the conventional dual damascene technique, via interconnects are typically formed substantially simultaneously with the overlying metallization. This technique requires that the holes through the insulator (the holes will eventually be filled with metal or other conductive material to form the via) be formed prior to the deposition of the layer of photoresist used in the subsequent patterning of overlying metallization.
By way of example,
FIG. 1A
is a cross sectional illustration of a semiconductor substrate
118
with underlying conductive layer
116
overlaid with a layer of insulator
108
having a via hole
115
. In the conventional damascene technique, the patterning of an overlying metallization layer that is to be formed is performed after via hole
115
is etched. Referring to
FIG. 1B
, prior to the deposition of the photoresist layer
102
used in patterning of the metal layer, a layer of anti-reflective coating
113
(known in the art and referred hereinafter as ARC) is conventionally deposited on the upper surface of the layer of insulator
108
. The ARC improves lithographic resolution. The ARC deposition operation results in a layer of ARC residue
114
within via hole
115
extending to approximately a height “t” above the conductive layer
116
. Subsequent to the formation of ARC layer
113
, a photoresist layer
102
is conventionally deposited upon the ARC layer
113
. The photoresist is then selectively exposed with a pattern from a mask. Depending on whether a positive or negative resist is used, either the exposed or unexposed portions are removed during development to create regions
110
and
112
. However, as can be seen in
FIG. 1B
, ARC layer
114
is substantially unaffected by the photoresist strip operation.
In order to form the plurality of trenches, both portions of ARC layer
113
and insulator
108
are removed in regions
110
and
112
unprotected by the photoresist. The removal is accomplished by exposing the wafer to a first etch process which breaks through the organic ARC layer
113
followed by a second etch to create the desired trench in the insulator
108
. However, the ARC residue
114
in via hole
115
reacts with etch by-products and forms a sidewall within via hole
115
. This sidewall within via hole
115
inhibits the action of the ARC and oxide etch operations and results in the creation of what is referred to in the art as a fence (
218
in FIG.
1
C). Fence
218
is generally substantially the same height “t” as the ARC residue discussed above.
FIG. 1C
is a cross sectional illustration of a semiconductor substrate
118
with underlying metallization
116
overlaid with a layer of insulator
108
subsequent to overlying metal lithography resist strip using conventional damascene techniques showing the presence of fence
218
.
As is known in the art, proper metal reflow is highly dependent upon the surface geometry of the surface onto which the metal is deposited. The presence of fence
218
disrupts the flow of metal which prevents a smooth flow of metal into via trench
212
. This disruption of the flow of metal into via trench
212
may result in the formation of voids within via hole
115
the presence of which substantially increases the electrical contact resistance of the via as formed. The voids may also present unacceptable reliability problems since all the current flowing through the via must be carried by the unvoided portions of the via. In this manner, high current densities through the unvoided portions of the via may result in electromigration of the via metal. Electromigration of the via metal may result in long term unacceptable Failure In Time (FIT) rates. In some cases, fence
218
may cause the formation of an electrical open by preventing sufficient metal flow into via hole
115
or via trench
222
to form an electrical contact with the underlying conductive layer
116
.
To address this problem, another prior art technique involves forming the trenches on the surface of the insulating layer prior to forming the via hole. However, the surface of the insulating layer is not planarized to facilitate etching of the via hole. In other words, no sacrificial material is deposited into the trenches for the purpose of planarizing the insulator surface to facilitate etching of the via hole. Accordingly, the ARC and photoresist materials, which are deposited to form the via mask to facilitate via etching, get deposited into the trenches and generally conform to the irregularities on the insulator surface. The depressions and projections on the irregular insulator surface renders the ARC and photoresist materials difficult to remove after the via hole etch. Additionally, it is also found that the depressions and projections on the irregular insulator surface present difficulty for photoresist to resolve small surface geometries.
Thus there is a need for techniques to eliminate the fences created by the conventional dual damascene technique as well as creating substantially planar surfaces suitable for resolution of small surface geometries.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention relates to semiconductor devices and more particularly, to an improved method of performing a dual damascene etch through a layer stack disposed above a substrate. According to one embodiment of the invention, the layer stack includes an underlying conductive layer and an insulating layer disposed above the underlying conductive layer. The method includes the following operative steps. First, forming a trench in a top surface of the insulating layer such that the trench is positioned over the underlying conductive layer and separated therefrom by insulating material at a bottom of the trench. Next, depositing flowable oxide over the top surface of the insulating layer and into the trench followed by planarizing the flowable oxide down to about a level of the top surface of the insulating layer. Finally, etching through the flowable oxide within the trench and through insulating material at the bottom of the trench down to the underlying conductive layer to form a via.
In another embodiment, a method of forming a via configured for connecting an underlying device layer and an overlying conductor of a layer stack is disclosed. In the disclosed embodiment, the overlying conductor is configured to be disposed in a trench formed in an
Feldner Klaus
Grewal Virinder
Schnabel Rainer Florian
Vollmer Bernd
Braden Stanton C.
Everhart Caridad
Siemens Aktiengesellschaft
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