Method of forming multi-layer wiring utilizing hydrogen silsesqu

Details Method of forming multi-layer wiring utilizing hydrogen silsesqu Method of forming multi-layer wiring utilizing hydrogen silsesqu

1996-07-12

1998-05-12

Utech, Benjamin

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

427569, 427120, 4272551, 4273762, 427377, 4274192, 205640, 20419222, B05D 302

Patent

active

057504032

ABSTRACT:
On a first insulating film covering a substrate, wiring layer patterns are formed and thereafter, a second insulating film of plasma CVD--SiO.sub.2 or the like is formed thereon. A hydrogen silsesquioxane resin film having a flat surface is spin-coated on the second insulating film. Thereafter, the resin film is subjected to a first heat treatment in an inert gas atmosphere to convert the resin film into a silicon oxide film of a preceramic phase. On this silicon oxide film, a third insulating film of plasma CVD--SiO.sub.2 or the like is formed. Thereafter, a second heat treatment is performed to convert the silicon oxide film of preceramic phase into a silicon oxide film of a ceramic phase, while preventing fine size projections from being formed on the surface of the silicon oxide film. Thereafter, a second wiring layer is formed on the third insulating film. It is possible to planarize an interlevel insulating film and improve a process yield.

REFERENCES:
patent: 4756977 (1988-07-01), Haluska et al.
patent: 5059448 (1991-10-01), Chandra et al.
patent: 5085893 (1992-02-01), Weiss et al.
patent: 5118530 (1992-06-01), Hanneman et al.
patent: 5145723 (1992-09-01), Ballance et al.
patent: 5336532 (1994-08-01), Haluska et al.
patent: 5370904 (1994-12-01), Mine et al.
patent: 5380567 (1995-01-01), Haluska
patent: 5399441 (1995-03-01), Bearinger et al.
patent: 5458912 (1995-10-01), Camilletti et al.
patent: 5481135 (1996-01-01), Chandra et al.
B.T. Ahlburn, et al., "A Non-Etch Back Spin on Glass for 0.5.mu.M Devices Using Hydrogen Silsesquioxane as a Replacement for Methylsiloxane", Jun. 7-8, 1994 VMIC Conference, pp. 120-122.
B.T. Ahlburn, et al., "Hydrogen Silsesquioxane-Based Flowable Oxide as an Element in the Interlevel Dielectric for Sub 0.5 Micron ULSI Circuits", Feb. 21-22, 1995 DUMIC Conference, pp. 36-42.
D.S. Ballance, et al., "Low Temperature Reflow Planarization Using a Novel Spin-On Interlevel Dielectric", Jun. 9-10, 1992 VMIC Conference, pp. 180-186.
D. Pramanik, et al., "Reliability of Multilevel Circuits Using Hydrogen Silsesquioxane FO.sub.x for Interlevel Dielectric Planarization", Jun. 8-9, 1993 VMIC Conference, pp. 329-331.
R. Dawson, et al., "Performance of Logic Devices Utilizing A Novel Spin-On Dielectric Planarization Process", Jun. 8-9, 1993 VMIC Conference, p. 218.

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