Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Self-aligned
Reexamination Certificate
2000-09-18
2002-08-20
Ho, Hoai V. (Department: 2818)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Self-aligned
C438S232000
Reexamination Certificate
active
06436783
ABSTRACT:
The present invention relates to a technique for improving a variation in threshold voltage of an MOS transistor through a long term use.
PRIOR ART
The conventional fabrication method for the MOS transistor will be explained with reference to
FIGS. 17-19
by taking an example of CMOS (complementary MOS transistor) fabrication processes.
As shown in FIG.
17
(
a
), after an isolation film
2
is formed on a silicon substrate
1
, a photo-resist
3
is provided on an n-MOS formation region so that an n-type impurity such as phosphorus is ion-implanted into a p-MOS formation region, whereby an n-type well
4
is formed. Subsequently, the photo-resist
3
remains and an impurity is ion-implanted for adjustment to a threshold voltage. Subsequently, as shown in FIG.
17
(
b
), a photo-resist
3
is provided on the p-MOS formation region for ion-implantation of a p-type impurity into the n-MOS formation region, whereby a p-type well
6
is formed. Subsequently, the photo-resist
3
remains and an impurity is ion-implanted for adjustment to a threshold voltage. Subsequently, a gate insulating film
7
is formed on a surface of an active region and a gate electrode material is then laminated thereon before patterning the same to form a gate electrode (FIG.
17
(
c
)).
As shown in FIG.
18
(
a
), a photo-resist
3
is provided on the p-MOS formation region for ion-implantation of an n-type impurity into the n-MOS formation region, whereby low impurity concentration source/don extension regions
13
. Subsequently, the photo-resist
3
remains and a p-type impurity is ion-implanted to form a pocket region
14
for preventing a short channel effect. Similarly, as shown in FIG.
18
(
b
), a p-type impurity and an n-type impurity are sequentially ion-implanted into the p-MOS formation region to form source/drain extension regions
16
and a pocket region
17
.
Subsequently, side walls
18
and side walls
19
are respectively formed to a gate electrode
20
and a gate electrode
21
(FIG.
19
(
a
)). Subsequently, a photo-resist
3
is provided on the n-MOS formation region before an ion-implantation of a p-type impurity is made into the p-MOS formation region, whereby a formation of the high impurity concentration source and drain regions
22
and an introduction of the impurity into the gate electrode
20
are concurrently made (FIG.
19
(
b
)). A photo-resist
3
is provided on the p-MOS formation region for ion-implantation of an n-type impurity into the n-MOS formation region, whereby a formation of the high impurity concentration source and drain regions
23
and an introduction of the impurity into the gate electrode
21
are concurrently made (FIG.
19
(
c
)). Thereafter, a heat treatment is made for activating the impurities in the source and drain regions and the gate electrode. As described above, the transistors forming the CMOS are formed.
The above processes are one example of the conventional fabrication method. Various methods such as methods of forming the source and drain regions have been on the investigation.
As the conventional CMOS has been used in a long term, then a phenomenon is caused that a threshold voltage Vth of the p-MOS varies. This phenomenon is more remarkable if the p-MOS has a surface channel structure and junctions of the source and drain region are shallow. This phenomenon is further remarkable if the scale down of the device is progressed and particularly if a gate length is not more than 0.2 micrometers and a threshold voltage of the transistor is low. In the past, the above phenomenon has rarely been considered. Notwithstanding, if the device is scaled down and a further high performance is required, then this is the important technical issue. The present inventor has made various investigations to the above phenomenon and could find out that the above phenomenon is cased by a slow trap of carrier in the channel region.
The region directly under the gate insulation film serves as the channel region of the transistor. Terminals of silicon forming this channel region is a dangling bond or bonded with hydrogen as shown in FIG.
16
(
a
). The dangling bond traps carrier to reduce the function of the channel region. In the prior art, usually, a hydrogen anneal is carried out to terminate the same with hydrogen to form Si—H bonding for removing the dangling bond. The Si—H bonding energy is relatively low, for which reason it is likely to cause elimination of hydrogen over time and then the dangling bond is again formed. As the dangling bond is increased over time with use of the transistor, then a probability of trapping the carrier in the channel region is increased over time. This phenomenon will hereinafter referred to as a slow trap. This slow trap once appeared, a threshold voltage varies over time and a drain saturation current is lowered over time.
In Japanese patent application No. 11-070723, the present inventor proposed a solution method against the above problem with the slow trap. This proposal is that side walls are provided, and ion-implantation of an impurity for forming the source/drain regions and subsequent heat treatment for activation thereto, before the fluorine ions are ion-implanted and then the heat treatment is made in the furnace anneal to covert the dangling bonds and Si—H bonds present on an interface of a gate oxide film and silicon of substrate into Si—F bonds.
This method improves the slow trap characteristic and makes transistor's characteristics stable in the long term use. Particularly, in the range of the gate length (source-drain distance) from about 0.18 micrometers or more, the long term reliability can be ensured and the designed transistor's characteristics can be obtained. This technique is extremely effective. However, if the above method is applied to the scaled down transistors such that the gate length is 0.15 micrometers, it is possible that the threshold voltage of the transistor varies. This will be described hereinafter.
In accordance with the above method, the fluorine is introduced after the heat treatment for activation to the source and drain regions, for which reason normally the introduction is made from outside of the side walls. Namely, the fluorine is introduced from positions relatively distanced from the channel region directly under the gate electrode, for which reason the introduction of a relatively large amount of fluorine is necessary for forming sufficient Si—F bonds in the channel region. The introduction of the large amount of fluorine ions, however, causes many inter-lattice silicon atoms introduced into the substrate upon fluorine implantation. The inter-lattice silicon atoms make pairs with the impurity of the channel region to cause an accelerating diffusion in the silicon substrate, whereby variation in the impurity concentration profile of the channel region is caused.
The pairs of the inter-lattice silicon atoms and the impurity have a large diffusion coefficient, and shows a high speed diffusion even at a low temperature. For example, the diffusion is caused at a formation temperature (700-800° C.) of an oxide film by a CVD method. The phenomenon of re-profile of the impurity concentration due to the pairs of the inter-lattice silicon atoms and the impurity is caused by the fact that the inter-lattice silicon atoms are present at a concentration of not less than a thermal equilibrium concentration and in this state the heat treatment is carried out. Namely, the impurity is not diffused in the normal heat treatment. Notwithstanding, in case of the presence of many inter-lattice silicon atoms generated in the ion-implantation process, such a large diffusion phenomenon as treated at a temperature not less than a normal heat treatment temperature is caused.
The variation in the impurity concentration profile as caused is not so problem if the transistor size is relatively large. But as the transistor is scaled down and for example, the gate length is not more than 0.15 micrometers, then the variation is problem. This will be described hereinafter.
As the scale of the transis
Hamanaka Nobuaki
Ono Atsuki
Ho Hoai V.
Vu David
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