Method of forming miniaturized polycrystalline silicon gate...

Details Method of forming miniaturized polycrystalline silicon gate... Method of forming miniaturized polycrystalline silicon gate...

2005-12-27

2005-12-27

Gurley, Lynne A. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S770000, C438S976000

Reexamination Certificate

active

06979635

ABSTRACT:
Ultra narrow and thin polycrystalline silicon gate electrodes are formed by patterning a polysilicon gate precursor, reducing its width and height by selectively oxidizing its upper and side surfaces, and then removing the oxidized surfaces. Embodiments include patterning the polysilicon gate precursor with an oxide layer thereunder, ion implanting to form deep source/drain regions, forming a nitride layer on the substrate surface on each side of the polysilicon gate precursor, thermally oxidizing the upper and side surfaces of the polysilicon gate precursor thereby consuming silicon, and then removing the oxidized upper and side surfaces leaving a polysilicon gate electrode with a reduced width and a reduced height. Subsequent processing includes forming shallow source/drain extensions, forming dielectric sidewall spacers on the polysilicon gate electrode and then forming metal silicide layers on the upper surface of the polysilicon gate electrode and over the source/drain regions.

REFERENCES:
patent: 5476802 (1995-12-01), Yamazaki et al.
patent: 5937319 (1999-08-01), Xiang et al.
patent: 6509275 (2003-01-01), Kamijima
patent: 6521500 (2003-02-01), Goto
Stanley Wolf and Richard N. Tauber, Silicon Processing For The VLSI Era, 1986, Lattice Press, vol. 1, pp. 191-194.

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