Method of forming micro-via

Details Method of forming micro-via Method of forming micro-via

2001-05-31

2002-05-28

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S678000, C438S637000, C438S672000

Reexamination Certificate

active

06395633

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90111679, filed on May 16, 2001.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a method of forming a micro-via. More particularly, the invention relates to a method of forming a micro-via that electrically connects neighbouring conductive layers in a printed circuit board.
2. Description of the Related Art
In the recent years, as the electronic products have been developed to be light, thin, short and small, the layout and fabrication of a printed circuit board (PCB) has necessarily been improved. To increase the layout density of the circuit, in addition to thinning the wires, a via used to electrically connect two neighboring conductive layers can be shrunk to operate the circuit with an enhanced efficiency.
In the prior art, a method of mechanically drilling through a hole is used to form a via hole in a printed circuit board. The minimum bore of the via hole is 0.2 mm. Being restricted by the accuracy of the mechanical process, the bore cannot be further decreased. Therefore, further wire refinement cannot be achieved. If a laser is used to for the hole drilling process, the bore can be further reduced.
As the integration of the electronic products increases, and the function thereof becomes more powerful the number of deposition layers is increased from one or two to five or six, and may even exceed ten. The electronic products can thus be accommodated in the printed circuit board with a more compact space. Accordingly, the bores of the laser drilled holes for high density interconnection becomes smaller and smaller. Once the position of the hole slightly shifts or deviates, the electric conduction is seriously affected. As a result, the reliability of the printed circuit board is lowered, and the fabrication cost is greatly increased due to the degradation of yield.
FIG. 1A
to
FIG. 1G
show the method of forming a via for connecting the neighboring conductive layers in a printed circuit board using a laser. In
FIG. 1A
, a substrate
10
is provided. The substrate
10
can be an inner substrate or an insulation layer. A patterned conductive wiring layer
12
is formed on the substrate
10
by photolithography and etching. In
FIG. 1B
, an insulation layer
14
is formed on the conductive wiring layer
12
and the substrate
10
. In
FIG. 1C
, a patterned conductive wiring layer
16
with openings
18
are formed on the insulation layer
14
.
In
FIG. 1D
, in the direction indicated by the arrows
20
, a laser drill operation is performed on the insulation layer
14
exposed by the openings
18
. In
FIG. 1E
, via holes
22
are formed in the insulation layer
14
to expose a surface of the conductive wiring layer
12
. In
FIG. 1F
, using screening printing, the via hole
22
is filled with a conductive material that serves as the vias
24
electrically connecting the conductive wiring layers
12
and
16
. Or, as shown in
FIG. 1G
, a via copper layer
26
is plated onto surfaces of the via holes
24
, followed by filling the via holes
24
with an insulation layer
28
. The via copper layer
26
provides the electric connection between the conductive wiring layers
12
and
16
.
The above laser drill through hole method introduces the following problems:
1. In the laser drilling process, if the laser is not precisely aligned with the opening of the conductive wiring layer, the insulation layer exposed by the opening cannot be effectively removed. Thus, conduction between two conductive wiring layers cannot be established, and the original wiring layout is altered.
2. The bore of the via can be reduced to less than 0.2 mm using a laser drilled through hole. However, the bore is still much larger than that of the via formed using photolithography, so there is still a limit to bore shrinkage when using the laser drill.
3. When filling the via hole with conductive material, if a cavity structure such as a bubble is formed in the conductive material, a popcorn structure is formed during heating. This damages the conductive wiring structure.
4. For the screen printing method, the conductive material filling the via hole uses many metal conductive particles mixed with liquid glue to increase fluidity. However, the material uniformity of the conductive material is consequently decreased to affect the stability of conduction.
SUMMARY OF THE INVENTION
The invention provides a method of forming a micro-via that provides electric connection between neighboring conductive wiring layers of a printed circuit board to resolve the problems occurring in the prior art. The method can be applied to fabrication and design of the layout of a circuit board. A substrate and a patterned conductive wiring layer on the substrate are provided. A copper layer is plated on surfaces of the substrate and the conductive wiring layer. A photoresist layer is formed on the plated copper layer. A part of the photoresist layer is removed to expose a part of the plated copper layer. Using the plated copper layer as a seed layer, a conductive pillar is formed on the exposed plated copper layer. The photoresist layer is removed, and the plated copper layer that is exposed after removing the photoresist layer. Another insulation layer is formed on surfaces of the substrate and the conductive pillars. A part of the insulation layer is removed to expose the conductive pillar. Another copper layer is plated onto surfaces of the conductive pillars and the insulation layer. A second photoresist layer is formed on the plated copper layer. A part of the second photoresist layer is removed to expose a part of the second copper layer. Again, using the second copper layer as a seed layer, a conductive pillar is formed on the exposed second copper layer. The second photoresist layer is removed.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 5925930 (1999-07-01), Farnworth et al.
patent: 5946600 (1999-08-01), Hurwitz et al.
patent: 6020640 (2000-02-01), Efland et al.
patent: 6100582 (2000-08-01), Omote et al.
patent: 6255126 (2001-07-01), Mathieu et al.
patent: 6300242 (2001-10-01), Ueda et al.
patent: 2001077145a (2001-03-01), None

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