Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-07-30
2003-09-16
Quach, T. N. (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S678000, C438S687000, C438S692000
Reexamination Certificate
active
06620726
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to the field of fabrication of integrated circuits, and, more particularly, to producing interconnect lines required in the various metallization layers of integrated circuits, such as CPUs, memory chips, and the like.
2. Description of the Related Art
In the fabrication of integrated circuits, such as CPUs, memory chips, application specific circuits and the like, it is generally necessary to provide one or more metal layers, so-called metallization layers, on the circuit substrate that serve to electrically connect the individual devices, such as transistor elements, capacitors, and the like, to one another. Depending on the complexity of the involved circuitry, the type of material used for the metallization and the dimensions of the metallization lines, which in turn are partly determined by the type of material and the available space on the substrate, a plurality of metallization layers may be necessary to provide the required functionality. The reproducible manufacturing of the individual metallization layers is of great importance for the performance and reliability of the integrated circuit, whereby the characteristics of each metallization line in every metallization layer must predictably lie within specified tolerances, as failure of a single line alone may jeopardize the complete circuit.
Since semiconductor manufacturers not only have to cope with requirements in terms of performance and reliability of the integrated circuits, but also in view of minimal production costs, the substrates on which the integrated circuits are fabricated are steadily increasing in diameter, since the majority of the process steps during manufacturing of the integrated circuit are carried out on a substrate basis rather than on a die basis so that a large number of chips may be processed in a single process step. Increasing substrate diameters, however, requires precise controlling of the process parameters to produce device features across the entire substrate that have characteristics as uniform as possible regardless of their location on the substrate.
Traditionally, aluminum has been used for metallization layers; however, semiconductor manufacturers have recently begun to employ copper as the metallization layer due to the superior characteristics of copper with respect to conductivity and electromigration, which are extremely important aspects for the production of integrated circuits with reduced feature sizes. One commonly used process for producing metallization layers is the so-called damascene process, where holes (also referred to as vias), trenches and/or other recessed portions are formed in an insulating layer, for example, a silicon dioxide layer, and are subsequently filled with the metal, such as copper. A preferred technique for supplying the copper to the vias and trenches is electroplating, since electroplating allows moderate deposition rates with a reasonable uniformity across large substrate areas compared to other deposition methods, thereby providing high cost-effectiveness. Electroplating requires, prior to deposition of the bulk material, the provision of a metallic seed layer, which is used to conduct electrical current during the bulk deposition. In some cases, the seed layer may also serve as a diffusion barrier layer and/or an adhesion layer for the bulk material, for example, copper, filled in the vias and trenches. In general, the seed layer is a very thin layer of metal having a thickness of about 100 nm and may be deposited by any known method, such as physical vapor deposition (PVD) or chemical vapor deposition (CVD). After deposition of the seed layer, the substrate is brought into contact with a electrolyte bath containing ionic compounds including metal ions of the required type and a voltage is established between an anode within the electrolyte bath and the substrate which acts as a cathode, whereby the seed layer serves to distribute the current across the entire substrate area. The metal layer is plated to an extent to form an overlying layer, thereby providing a metal layer that fills the trenches and vias and extends slightly above these device features. Typically, the thickness of the metal layer is on the order of 1 &mgr;m.
After deposition of the metal layer, excess metal has to be removed to complete the patterning of metal lines. In the damascene process, chemical mechanical polishing (CMP) has proven to be the preferred technique for removing excess metal. During the chemical mechanical polishing, the combined action of a chemical removal agent and an abrasive is used to commonly react and grind and polish the exposed metal surface, thereby planarizing the residual substrate surface. Although CMP is very successfully employed in fabricating metallization layers, establishing a CMP technique that provides minimum non-uniformity across the entire substrate area has been found to be a challenging task for process engineers, especially for large-diameter substrates. In providing a uniform planarized surface after removal of excess metal, it is not only important during a CMP process to keep the removal of the metal and the surrounding dielectric material, which are also referred to as dishing and erosion, within specified tolerances regarding the various feature patterns on a single chip, but to maintain these specified tolerances in view of dishing and erosion also at locations that are spaced more distantly, for example at the center and the periphery of the substrate.
With reference to
FIGS. 1
a
and
1
b
, a typical metallization pattern is schematically depicted to demonstrate the effects of dishing and erosion during CMP. In
FIG. 1
a
, a metallization structure
100
comprises an insulating layer
101
having formed therein a single metal line
102
and a plurality of closely spaced metallization lines
103
. The insulating layer
101
may, for example, be made of silicon dioxide and the metal lines
102
and
103
may primarily comprise copper. The metallization structure
100
may be positioned, for example, at a central location of the substrate. While the metallization structure
100
is subjected to the CMP process, insulating material is removed from the initial insulating layer
101
as represented by the arrows E. This removal of material compared to the initial material layer is referred to as erosion and may depend on the type of feature pattern formed in the insulating layer
101
. For example, the erosion in the vicinity of the single metal line
102
may be significantly smaller than in the vicinity of the plurality of metal lines
103
. Additionally, copper within the metal lines
102
and
103
is removed more intensely than material of the surrounding insulating layer
101
. This excess material removal process within the metal lines
102
and
103
is referred to as “dishing” and is indicated by D in
FIG. 1
a.
FIG. 1
b
schematically depicts a metallization structure
150
comprising an insulating layer
151
and metal lines
152
and
153
formed in the insulating layer
151
. In principle, the metallization structure
150
corresponds to the structure
100
, but is, however, located at the periphery of the substrate. Since in the CMP process under consideration the removal rate at the periphery of the substrate is reduced compared to a central location, erosion and dishing in the metallization structure
150
is reduced compared to the structure
100
. Accordingly, the metallization lines
152
,
153
exhibit an increased cross-section and, therefore, an enhanced conductivity compared to the metal lines
102
,
103
. In order to secure reliability and performance of integrated circuits fabricated all over the substrate area, design rules must take into account the above-mentioned non-uniformities of the metal lines in different substrate areas. This contributes to process complexity and, thus, production costs.
In view of the above problems, there is a need for an improved process sequence for forming metallization
Marxsen Gerd
Nopper Markus
Preusse Axel
Advanced Micro Devices , Inc.
Quach T. N.
Williams Morgan & Amerson P.C.
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