Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-07-19
2001-07-10
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S597000, C438S620000, C438S636000, C438S711000, C438S720000, C216S078000
Reexamination Certificate
active
06258727
ABSTRACT:
FIELD OF INVENTION
The present invention relates to the manufacture of semiconductor integrated circuits (ICs) and more particularly to a method of forming metal lands at the M0 level by plasma etching with a non selective chemistry.
BACKGROUND OF THE INVENTION
In the manufacture of semiconductor integrated circuits, and particularly in Dynamic Random Access Memory (DRAM) chips, a metal interconnect at the first level, referred to herein below as the M0 level, is extensively used to address memory cells of the chip. In essence, it is used to interconnect the source regions of all the Insulated Gate Field Effect Transistors (IGFETs) driven by the same Word Line (WL) and the gate conductors of all the IGFETs driven by a same Bit Line (BL) to their respective driving IGFET at the chip periphery. Each word line consists of a metal land which is formed at the M0 photolithography level.
The essential steps of a conventional M0 metal lands formation process will be briefly described by reference to FIG.
1
and
FIGS. 2A
to
2
E. After these steps have been completed, the metal contacts and lands of the M0 interconnect scheme are fabricated.
FIG. 1
schematically illustrates a state-of-the-art semiconductor structure
10
which is a part of a wafer at the initial stage of the M0 metal land formation process. Structure
10
basically comprises a silicon substrate
11
with diffused regions formed therein and a plurality of gate conductor stacks
12
formed thereon. A gate conductor stack consists of a composite SiO2/doped polysilicon/tungsten silicide structure. At the chip surface, two different zones are to be considered. First, the “array” zone wherein the memory cells are fabricated. Each elementary memory cell is comprised of an IGFET and its associated capacitor that is formed in a deep trench as standard. In the other zone referred to as the “support”, one can find addressing and driver circuits. Structure
10
is coated with a boro-phosphosilicate-glass (BPSG) layer
13
and a tetra-ethyl-ortho-silicate (TEOS) oxide layer
14
above of it. These layers are conformally deposited onto structure
10
by LPCVD as standard. As apparent in
FIG. 1
, structure
10
has a substantially planar surface.
Now two types of contact holes are created depending upon their location at the chip surface. First, contact holes referred to as CB holes bearing numeral
15
in
FIG. 2A
are etched through layers
13
and
14
in the “array” area. A doped polysilicon layer
16
is conformally deposited onto structure
10
to fill contact hole
15
in excess. Next, the doped polysilicon is etched in a plasma until the TEOS layer
14
surface is reached. Then, the etching is continued to produce a recess (CB recess) in the polysilicon fill
16
as shown in FIG.
2
A. CB recesses will be subsequently filled with metal to produce the desired M0 metal lands for the word lines. This etching is determined by time and is very critical because of its sensitivity to the etch duration. Because of product non-uniformities, this over etching is carefully conducted in order not to reach the TEOS/BPSG interface. The purpose of this step as a whole is to produce conductive studs
16
that will allow an electrical contact between M0 metal lands and N type diffused regions (e.g. a source region common to two adjacent IGFETs as illustrated in
FIG. 2A
) in the substrate
11
. Contact holes
17
and
18
are etched through layers
13
and
14
in the “support” area at desired locations to expose gate conductor stacks of IGFETs and diffusion regions of the substrate
11
respectively and will be referred to as the CG and CD holes. The resulting structure is shown in FIG.
2
A.
Now, turning to
FIG. 2B
, structure
10
is coated first with a 90 nm thick anti-reflective coating (ARC) layer
19
which fills all contact holes
15
,
17
and
18
, then with a 850 nm thick photoresist material
20
. Adequate chemicals are supplied by SHIPLEY USA, Malborough, Mass., USA under references BARL 900 and UV2HS respectively. After deposition, the photoresist layer
20
is baked, exposed and developed as standard to leave a patterned layer, that will be referred to herein below as the M0 mask. The purpose of this mask is to define the locations of contacts and lands of the first interconnect level at the surface of structure
10
.
After the M0 mask
20
has been defined, the process continues with an etch step to remove 270 nm of TEOS layer
14
at locations not protected by said M0 mask. To that end, the wafer is placed in the chamber of an AME 5200 MxP+RIE etcher, manufactured by Applied Materials, Santa Clara, Calif., USA, where it is etched with the two-step process detailed below.
The first step so-called “ARC OPEN”, etches the ARC layer
19
down to the TEOS layer
14
top surface. This step is performed with a CF4 chemistry according to the following operating conditions given below.
Step 1:
CF4
40 sccm
Pressure
45 mTorr
RF Power
300 Watt
Mag. field
40 Gauss
Wall temp.
15° C.
Cathode temp.
15° C.
He cooling
14 Torr
Etch time
80 s
At this stage of the M0 land fabrication process, the structure
10
is shown in FIG.
2
C. As apparent in
FIG. 2C
, openings in M0 mask
20
have tapered side walls. This will widen the M0 land size reducing thereby the process window of the previous M0 lithographic step.
The second step etches about 270 nm of the TEOS layer
14
to produce the desired recesses wherein the M0 metal lands will be subsequently formed. Process parameters for step 2 read as follows:
Step 2:
CHF3
35 sccm
CF4
25 sccm
Argon
150 sccm
Pressure
160 mTorr
RF Power
1000 Watt
Mag. field
0 Gauss
Wall temp
15° C.
Cathode temp.
15° C.
He cooling
14 Torr
Etch time
34 s
The resulting structure is shown in
FIG. 2D
, where recesses are referenced
21
and
22
depending they are located in the “array” or “support” region. They will be referred to as land recesses
21
/
22
herein below.
Unfortunately, the above-described two-step etch process is not satisfactory. As mentioned above, step 1 produces tapered contact holes because the CF4 chemistry is very sensitive to ARC layer
19
thickness variations (its thickness can vary in the 700-1100 nm range), so that land recesses
21
/
22
dimensional can significantly vary center-to-edge of a same wafer. This can be avoided by a very long etch duration, but at the potential risk of a degradation in the contact hole side wall sharpness. Tapered contact holes are a potential source of electrical shorts occurring between two adjacent M0 metal lands, in turn resulting in a high number of failed cells. On the contrary, if in an attempt to avoid such shorts, contact holes are under etched, too resistive M0 metal lands would be produced. In addition, the chemistry of step 2 has different etch rates between ARC, polysilicon and TEOS materials producing similar resistance related problems.
Now turning to the right part of
FIG. 2C
, in the “support” region, it is clear that CG and CD contact holes
17
and
18
are still filled with ARC material. During step 2, as the CHF3/CF4/Ar chemistry etches TEOS SiO2 much more faster than ARC material and because contact holes
17
and
18
are tapered, the ARC material acts as a mask and blocks etching of the TEOS SiO2 material of layer
14
at their close proximity. As a result, TEOS SiO2 fences
23
remain around ARC filled contact holes
17
and
18
and depressions
24
are also are created at these locations as visible in FIG.
2
D. The same particularities occur in the “array” region as apparent in the left part of FIG.
2
D. It can be also noticed that because the chemistry of step 2 is unable to etch polysilicon stud
16
, the latter is higher than the M0 level.
At this stage of the process, the remaining ARC and photoresist materials are removed using a conventional strip process. Then, a 25 nm thick dual adhesion layer of titanium/titanium nitride (Ti/TiN) forming a liner is deposited onto the wafer by sputtering. This is followed by the blanket deposition of a tungsten (W) layer by Chemical Vapor Deposition (CVD). Next, the wafer is chem-mech
International Business Machines - Corporation
Malsawma Lex H.
Smith Matthew
LandOfFree
Method of forming metal lands at the M0 level with a non... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming metal lands at the M0 level with a non..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming metal lands at the M0 level with a non... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2455375