Static information storage and retrieval – Addressing
Reexamination Certificate
2000-02-08
2001-04-03
Elms, Richard (Department: 2824)
Static information storage and retrieval
Addressing
C365S188000, C365S189070, C365S189080
Reexamination Certificate
active
06212124
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a static RAM (random access memory) for use in digital computer systems. More specifically, the present invention relates to a static RAM which features an inclusion of improved word line driving circuitry which is shared by all the memory cells provided in the RAM. The memory cell comprises four MOSFETs (metal oxide semiconductor field effect transistors) which have no load.
2. Description of the Related Art
Memory cells used in digital information processing systems are generally classified into two types: one is dynamic memory cells and the other is static memory cells. The static memory is able to retain the binary data stored therein as long as power is applied thereto. That is, the static memory cell requires no overhead circuitry for periodical refresh as do the dynamic memory cell. Although the static RAM features high speed of memory access time, i.e., the time required to store and/or retrieve a particular bit(s) in the memory array, the area-efficiency of the memory array is poor relative to the dynamic RAM. That is, the number of stored data bits per unit area is one of the key design criteria that determine the overall storage capacity and hence the memory cost per bit. In order to improve the area-efficiency of a static RAM, a four-transistor having no load has been proposed as mentioned below.
Before turning to the present invention, it is deemed advantageous to briefly describe conventional static RAMS with reference to
FIG. 1
, which is provided with four-transistor memory cells without any load and is disclosed in U.S. Pat. No. 4,796,227.
As shown in
FIG. 1
, a memory cell
10
includes a pair of cross-coupled transistors
12
and
14
comprising a circuit having two stable states. The selected state is retained by charge or potential on the gates of the transistors
12
and
14
. The memory cell
10
further includes two bit line coupling transistors
16
and
18
. The channel types of the transistors
12
and
14
are opposite to those of the transistors
16
and
18
. That is, in the case where the transistors
12
and
14
are n-channel types as shown in
FIG. 1
, the transistors
16
and
18
are p-channel types and vice versa. The sources of the transistors
12
and
14
are grounded, and the drains thereof are respectively coupled to the drains of the transistors
16
and
18
. The gates of the transistors
12
and
14
are respectively coupled to the drains of the transistors
14
and
12
. On the other hand, the sources of the transistors
16
and
18
are respectively coupled to bit lines BL
0
and BL
1
, and the gates thereof are both coupled to a word line WL
1
.
For the convenience of simplifying the descriptions, it is assumed that the memory cell
10
is in a standby mode (viz., the memory cell
10
is not being read or written). Further, assuming that the potentials at nodes
20
and
22
are respectively high and low, which indicates that the memory cell
10
stores one of two binary data (vis., logic “1” or “0”). In the standby mode, the potential on the bit lines BL
0
and BL
1
is at Vdd, and a bias voltage is applied to the word select line WL
1
. Under the above-mentioned assumption, only the transistor
12
is in a conducting state, and the other transistors
14
,
16
, and
18
are in non-conducting states. More specifically, the transistors
14
,
16
, and
18
are not in a fully non-conducting state, and a bias potential is applied to the word select line WL
1
which is sufficient to cause small currents I
3
and I
OFF-P
to flow through the transistors
16
and
18
, respectively. The small current I
OFF-P
is used to compensate for a leak current I
OFF-N
flowing through the transistor
14
, which would otherwise result in a loss of charge (vis., high potential) at the node
20
. In the above, since the transistor
12
is assumed to be conducting, the current I
3
, flowing through the transistor
16
, which in the ideal case, is equal to the current I
OFF-P
, is wasted. However, the current I
3
is very small, the overall power dissipation of the memory cell
10
is not significantly effected.
On the contrary, if the potentials on the nodes
20
and
22
are respectively low and high, the memory cell
10
stores the other binary information. In this case, it is understood that the leak current flowing through the transistor
12
should be compensated for in the same manner as mentioned above.
The bias current I
3
is set with the aid of two “current mirror” circuits. The combination of transistors
24
and
16
forms a first current mirror circuit wherein the load current I
3
is proportional to a current I
2
in a bias circuit
26
times a geometric width ratio which is proportional to the ratio of the widths of the channels of the transistors
24
and
16
. On the other hand, transistors
28
and
30
form a second current mirror circuit in which the current I
2
is proportional to a current I
1
applied from a constant current source (not shown) times a second geometric width ratio which is proportional to the ratio of the widths of the channels of the transistors
28
and
30
. Accordingly, the current I
OFF-P
, which is ideally equal to the current I
3
, is able to maintain the potential on the node
20
by compensating for the leak current I
OFF-N
.
During the standby mode, each of the bit lines BL
0
and BL
1
is at Vdd as mentioned above. Further, in this mode, there are no reading and writing operations, and AND gate
32
issues no coincidence signal in order that a transistor
34
is conducting and a transistor
36
is non-conducting. Accordingly, the bias voltage continues to be applied to the memory cell
10
by way of the word line WL
1
. The AND gate
32
and the transistors
34
and
36
form a switch.
To read the memory cell
10
, the potential on the word line WL
1
is lowered to ground in response to the change of on-and-off state of the transistors
34
and
36
, which is caused by the coincidence issued from the AND gate
32
. Accordingly, the transistors
16
and
18
are brought into conducting state, which exhibits a potential difference on the bit lines BL
0
and BL
1
. This potential difference is detected using a sense amplifier (not shown) and hence, the binary data stored in the memory cell
10
is read.
On the other hand, to change the state of the memory cell
10
(viz., the transistors
12
and
14
are respectively turned off and on). the potential on the word the WL
1
is lowered to ground as just mentioned above. Thereafter, a low signal is applied through the transistor
18
to turn off the transistor
12
whose gate is coupled to the node
20
.
With the arrangement shown in
FIG. 1
, the constant current source (not shown) providing the current I
1
and its associated diode connected transistor
28
are shared by all of the memory cells. As a result, the prior art of
FIG. 1
has encountered the problem that the peripheral circuitry of the memory cells undesirably occupies a considerable area on the chip. This is because the transistors
24
,
30
,
34
, and
36
and the AND gate
32
should be provided for each of the word lines. In view of the ever-increasing demand for increase in the memory capacity of static RAM up to hundreds of thousands and more, it is highly preferable to reduce the area occupied by the peripheral circuitry of the memory cells. Further, the current is applied to the memory cell which comprises n-channel transistors
12
, and
14
having large temperature-depending characteristics. Therefore, the large currents are inevitably needed when the memory chip is placed in high temperature environments because the current applied to each of the memory cells should be previously set to cover the condition of low ambient temperature.
SUMMARY OF THE INVENTION
It is therefore an object of the present to provide a static RAM featuring high area-efficiency, i.e., enabling it to increase the number of stored data bits per unit area in order to increase the overall storage capacity and he
Elms Richard
Hutchins, Wheeler & Dittmar
NEC Corporation
Nguyen Tuan T.
LandOfFree
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