Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
2011-08-16
2011-08-16
Cao, Phat X (Department: 2814)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C257S613000, C257SE21459, C257SE21460, C257S236000, C438S478000, C438S479000, C438S099000, C438S142000, C438S149000, C438S144000, C438S400000
Reexamination Certificate
active
07998828
ABSTRACT:
A method of forming a metal ion transistor comprises forming a first electrode in a first isolation layer; forming a second isolation layer over the first isolation layer; forming a first cell region of a low dielectric constant (low-k) dielectric over the first electrode in the second isolation layer, the first cell region isolated from the second isolation layer; forming a cap layer over the second isolation layer and the first cell region, at least thinning the cap layer over the first cell region; depositing a layer of the low-k dielectric over the second isolation layer and the first cell region; forming metal ions in the low-k dielectric layer; patterning the low-k dielectric layer to form a second cell region; sealing the second cell region using a liner; and forming a second electrode contacting the second cell region and a third electrode contacting the second cell region.
REFERENCES:
patent: 5753947 (1998-05-01), Gonzalez
patent: 5792569 (1998-08-01), Sun et al.
patent: 5970336 (1999-10-01), Wolstenholme et al.
patent: 5986858 (1999-11-01), Sato et al.
patent: 6110751 (2000-08-01), Sato et al.
patent: 6236059 (2001-05-01), Wolstenholme et al.
patent: 6376284 (2002-04-01), Gonzalez et al.
patent: 6424041 (2002-07-01), Oashi et al.
patent: 6436817 (2002-08-01), Lee
patent: 6544801 (2003-04-01), Slaughter et al.
patent: 6661703 (2003-12-01), Ikeda
patent: 6713830 (2004-03-01), Nishimura et al.
patent: 6721201 (2004-04-01), Ikeda
patent: 6757187 (2004-06-01), Hoenigschmid
patent: 6760251 (2004-07-01), Hidaka
patent: 6764894 (2004-07-01), Lowrey et al.
patent: 6869883 (2005-03-01), Chiang et al.
patent: 6943393 (2005-09-01), Miethaner et al.
patent: 6943394 (2005-09-01), Yoshihara et al.
patent: 6944049 (2005-09-01), Hoenigschmid et al.
patent: 6980468 (2005-12-01), Ounadjela
patent: 6992342 (2006-01-01), Motoyoshi et al.
patent: 7038261 (2006-05-01), Horii
patent: 7482288 (2009-01-01), Penka et al.
patent: 2002/0044396 (2002-04-01), Amano et al.
patent: 2003/0061958 (2003-04-01), Zhang
patent: 2003/0063491 (2003-04-01), Ikeda
patent: 2004/0160810 (2004-08-01), Deak et al.
patent: 2004/0183647 (2004-09-01), Arai et al.
patent: 2004/0217481 (2004-11-01), Farrar
patent: 2005/0151127 (2005-07-01), Iwata et al.
patent: 2007/0023917 (2007-02-01), Yamada
patent: 2008/0173975 (2008-07-01), Chen et al.
patent: 2002064190 (2002-03-01), None
U.S. Appl. No. 11/951,579, filed Dec. 6, 2007, Notice of Allowance and Fees Due dated Feb. 24, 2010.
U.S. Appl. No. 11/951,579, filed Dec. 6, 2007, Amendment to Office Action, filed Nov. 23, 2009.
U.S. Appl. No. 11/951,579, Office Action dated Aug. 21, 2009.
Tondelier et al., “Metal/organic/metal Bistable Memory Devices”, Applied Physics Letters, Dec. 2004,vol. 85, No. 23.
Ma et al., “Organic Nonvolatile Memory by Controlling the Dynamic Copper-Ion Concentration Within Organic Layer”, Applied Physics Letters, Jun. 2004, vol. 84, No. 24.
U.S. Appl. No. 11/951,579, filed Dec. 6, 2007, Notice of Allowance dated Aug. 11, 2010.
U.S. Appl. No. 11/951,579, filed Dec. 6, 2007, Notice of Allowance dated Jun. 14, 2010.
U.S. Appl. No. 11/625,607, filed Jan. 22, 2007, Notice of Abandonment dated Jan. 27, 2010.
U.S. Appl. No. 11/625,607, filed Jan. 22, 2007, Notice of Allowance and Fees Due, dated Oct. 6, 2009.
U.S. Appl. No. 11/625,607, filed Jan. 22, 2007, Preliminary Amendment filed Jul. 22, 2008.
U.S. Appl. No. 11/625,607, filed Jan. 22, 2007, Notice of Non-Compliant Amendment dated Jul. 21, 2008.
U.S. Appl. No. 11/625,607, filed Jan. 22, 2007, Preliminary Amendment filed Jun. 26, 2008.
Chen Fen
Fischer Armin
Abate Joseph P.
Cao Phat X
Garrity Diana C
Hoffman Warnick LLC
Infineon Technologies North America
LandOfFree
Method of forming metal ion transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming metal ion transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming metal ion transistor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2674267