Method of forming metal/high-k gate stacks with high mobility

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257SE29128

Reexamination Certificate

active

07115959

ABSTRACT:
The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010charges/cm2or less, a peak mobility of about 250 cm2/V-s or greater and substantially no mobility degradation at about 6.0×1012inversion charges/cm2or greater.

REFERENCES:
patent: 6911381 (2005-06-01), Agarwal et al.
patent: 2003/0129826 (2003-07-01), Werkhoven et al.
patent: 2004/0188778 (2004-09-01), Aoyama
Ku, V. et al. “Low Tinv (≦1.8 nm) Metal-Gated MOSFETs on SiO2Based Gate Dielectrics for High Performance Logic Applications.”Int. Conf. SSDMvol. Tokyo, Japan p. 730-731 (2003).
Hiratani, Masahiko et al. “Effective Electron Mobility Reduced by Remote Charge Scattering in High-k Gate Stacks.”Jpn. J. Appl. Phys. vol. 41 p. 4521-4522 (2002).
Fischetti, Massimo et al. “Effective Electron Mobility in Si Inversion Layers in Metal-Oxide-Semiconductor Systems with a High-k Insulator: The Role of Remote Phonon Scattering.”J. Appl. Phys. vol. 90, No. 9 p. 4578-4601 (2001).
Callegari, A. et al. “W/HfO2Gate Stacks with Tinv˜1.2nm and Low Charge Trapping.”Int. Conf. SSDMp. 808-809 (2003).

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