Method of forming metal/dielectric multi-layered interconnects

Details Method of forming metal/dielectric multi-layered interconnects Method of forming metal/dielectric multi-layered interconnects

2001-10-12

2003-03-11

Cao, Phat X. (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S624000, C438S626000, C438S683000, C438S769000

Reexamination Certificate

active

06531385

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90101610, filed on Jan. 29, 2001.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of forming a multi-layered interconnect. More particularly, the present invention relates to a method of forming a metal/dielectric multi-layered interconnect.
2. Description of Related Art
In the manufacturing of VLSI circuits, dielectric layers are mostly formed by chemical vapor deposition (CVD). One major advantage of using CVD is good step coverage which makes CVD a popular candidate for inter-metal dielectric process.
FIG. 1
is a schematic cross-sectional view showing a conventional metal/dielectric multi-layer interconnect. As shown in
FIG. 1
, a fluorinated silica glass (FSG) dielectric layer
102
is formed over a substrate
100
whereon a conductive layer
104
is formed. A cap layer
110
is formed over the surface of the dielectric layer
102
. A via plug
106
is formed above the conductive layer
104
. The surface of the conductive layer
104
and the surface of the substrate
100
are coated by a silicon oxide protective layer
108
. A cap layer
110
is formed over the upper surface of dielectric
102
. In addition, a barrier layer
105
is formed before formation of plug
106
.
Conventional multi-layered interconnects are formed using fluorinated silica glass (FSG) as the dielectric material in a CVD. However, fluorine ions may react readily with metallic elements once they are released from the FSG material. Moreover, FSG material is less stable than silicon dioxide (SiO
2
) and may lead to subsequent interconnect reliability problems. In addition, silicon oxide is frequently used as a protective layer for a conductive layer. A silicon oxide layer is thus only a weak barrier for fluorine ions and hence fluorine ions can penetrate through the silicon oxide layer and attack the conductive layer. Furthermore, the cap layer covering the FSG dielectric layer is a must and generally formed by a TEOS, SiO
2
or SiO
2
+ plasma treatment. If the need for forming a cap layer over the FSG dielectric layer can somehow be removed, some cost and production time can be saved.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a method for forming a metal/dielectric multi-layered interconnect capable of preventing damages to a conductive layer due to the use of fluorinated silica glass (FSG) material.
To achieve these and other advantages and in accordance with the purpose of the invention, the invention provides a method for forming a metal/dielectric multi-layered interconnect. A conductive layer is formed over a substrate. A protective layer is formed over the conductive layer. A high-density plasma fluorinated silica glass (HDP-FSG) film is formed over the substrate by performing UDP chemical vapor deposition with a low bias-voltage power. A HDP-FSG layer is formed over the HDP-FSG film by performing HDP chemical vapor deposition with a high bias-voltage power. A silicon oxynitride (SiON) is formed over the FSG layer. A via opening is formed in the FSG layer above the conductive layer. A barrier layer is formed over the substrate. Tungsten is deposited over the substrate to fill the via opening.
In this invention, a protective layer that serves as a barrier to the highly a penetrating fluorine ions is formed over the conductive layer. HDP chemical vapor deposition using a low bias-voltage power is next conducted to form a HDP-FSG dielectric layer so that damages to the protective layer are minimized. In the subsequent step, HDP chemical vapor deposition using a high bias-voltage power is conducted to form a HDP-FSG dielectric layer having a higher Si—F bonding stability and a lower moisture content. In addition, a silicon oxynitride layer is formed over the planarized FSG dielectric layer as a cap layer. The silicon oxynitride layer can serve not only as a barrier that isolates the FSG dielectric layer, but also as an anti-reflection coating in a photolithographic process for forming a via opening. Consequently, some cost and production time can be saved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5946601 (1999-08-01), Wong et al.
patent: 6400023 (2002-06-01), Huang

Affiliated with

Also associated with

Rating

Method of forming metal/dielectric multi-layered interconnects does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming metal/dielectric multi-layered interconnects, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming metal/dielectric multi-layered interconnects will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3026160