Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2000-08-30
2002-04-23
Powell, William A. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S745000, C438S753000, C438S756000
Reexamination Certificate
active
06376380
ABSTRACT:
TECHNICAL FIELD
This invention relates generally to methods of forming memory circuitry, for example memory circuitry comprising a buried bit line array of memory cells.
BACKGROUND OF THE INVENTION
Conventional dynamic random access memory (DRAM) fabrication utilizes either a buried bit line or a non-buried bit line construction. With buried bit line constructions, bit lines are provided in elevational close proximity to the bit line contacts of the memory cell field effect transistors (FETs), with the cell capacitors being formed horizontally over the top of the word lines and the bit lines. With non-buried bit line constructions, deep vertical contacts are typically made through a thick insulating layer to the memory cell FETs, with the capacitor constructions being provided over the word lines and beneath the bit lines.
While this invention was principally motivated in fabricating buried bit line constructions and associated with DRAM, aspects of the invention are applicable to fabrication of other memory circuitry.
SUMMARY
The invention includes methods of forming memory circuitry, including methods of forming memory circuitry comprising a buried bit line array of memory cells. In one implementation, a method of forming memory circuitry comprising a buried bit line array of memory cells includes, in a single planarizing step, planarizing storage node contact opening plugging material and bit line trench plugging material to insulating material to form bit lines and storage node contacts which are electrically isolated laterally from one another by the insulating material.
In one implementation, a method of forming memory circuitry comprising a buried bit line array of memory cells, includes forming word lines over a semiconductor substrate. An insulating layer is formed over the substrate and over the word lines. Using a single photomasking step, bit line contact openings and capacitor storage node contact openings are patterned and formed into the insulating layer. After forming the bit line contact openings and the storage node contact openings, bit line trenches are formed into the insulating layer and which overlie and connect with the bit line contact openings.
Other aspects are contemplated.
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Narasimhan Raj
Tang Sanh D.
Powell William A.
Wells St. John P.S.
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