Method of forming low-resistive contact to N+/P+ preohmic region

Details Method of forming low-resistive contact to N+/P+ preohmic region Method of forming low-resistive contact to N+/P+ preohmic region

1988-12-27

1991-12-03

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437192, 437193, 437203, 437202, 148DIG19, 148DIG26, 148DIG147, H01L 2140, H01L 21283

Patent

active

050700383

ABSTRACT:
A method of forming low-resistive contact to at least two preohmic regions formed in a silicon substrate having a thick insulating layer thereon, including the steps of depositing a polysilicon on the insulating layer, performing an anisotropic etch for opening the preohmic regions, sputter-depositing a titanium deposit, the deposited titanium having electrical disconnections on the vertical side-walls of the opening regions, siliciding the titanium deposit, and depositing a metal silicide deposit for preventing electrical disconnections. Another embodiment uses a sputter-deposited titanium silicide deposit instead of titanium silicide. Still another embodiment includes the step of forming holes by an anisotropic etch, depositing polysilicon in the holes and on the insulating layer, sputter-depositing an titanium deposit, forming an titanium silicide deposit, and depositing a metal silicide deposit.

REFERENCES:
patent: 4364166 (1982-12-01), Crowder et al.
patent: 4619035 (1986-10-01), Hotta et al.
patent: 4720908 (1988-01-01), Wills
patent: 4751198 (1988-06-01), Anderson
patent: 4784973 (1988-11-01), Stevens et al.
patent: 4818723 (1989-04-01), Yen
patent: 4897709 (1990-01-01), Yokoyama et al.
patent: 4904620 (1990-02-01), Schmitz

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