Method of forming low resistance contact structures in vias arra

Details Method of forming low resistance contact structures in vias arra Method of forming low resistance contact structures in vias arra

1997-08-05

2000-01-11

Quach, T. N.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438625, 438627, 438637, 438714, 438722, 438725, H01L 2128, H01L 2131

Patent

active

060135743

ABSTRACT:
A method of forming low resistance contact structures in vias arranged between interconnect levels is provided. The method involves interconnect lines having an anti-reflective layer formed thereupon. An interlevel dielectric layer is formed over the interconnect lines. A photoresist layer is formed over the interlevel dielectric layer and patterned to define via locations. During via etch, an organic (carbon-based) polymer layer forms upon the anti-reflective-coated interconnect lines at the bottoms of the vias. The photoresist and the etch byproduct polymer layers are then removed using a dry etch process which employs a forming gas comprising nitrogen and hydrogen. A native oxide layer subsequently forms upon the anti-reflective-coated interconnect lines when exposed to oxygen. The native oxide layer is then removed, along with any residual etch byproduct polymer, during a sputter etch procedure. Each resulting via is substantially void of polymer and oxide residue so as to present a clean via area which allows ready adherence of a plug material to the anti-reflective coating.

REFERENCES:
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patent: 5327011 (1994-07-01), Iwamatsu
patent: 5354712 (1994-10-01), Ho et al.
patent: 5420070 (1995-05-01), Matsuura et al.
patent: 5567271 (1996-10-01), Chu et al.
"Silicon Processing For The VLSI Era," vol. 1, Process Technology, Wolf, et al., 1986, Chapter 16, pp. 580-581.

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