Method of forming low capacitance interconnect structures on sem

Details Method of forming low capacitance interconnect structures on sem Method of forming low capacitance interconnect structures on sem

1997-09-17

1999-06-01

Everhart, Caridad

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438424, 438437, 438439, H01L 21441

Patent

active

059083182

ABSTRACT:
Disclosed herein is a method for forming an interconnect line having low conductor line capacitance between devices formed on an integrated circuit. The method comprises the steps of depositing a removable planarizing layer over fabricated device on the integrated circuit, depositing a first oxide layer over the planarizing layer, etching pillar shafts through the planarizing layer and the first oxide layer for the formation of pillars, depositing a second oxide layer over the first oxide layer filling the pillar shafts to form the pillars, etching contact shafts through the planarizing layer, the first oxide layer, and the second oxide layer to expose contacts for a first device and a second device formed on the integrated circuit, forming an electrical coupling between the contacts of the first device and the second device, etching through the planarizing layer, the first oxide layer, and the second oxide layer to provide accesses to the planarizing layer, removing the planarizing layer to form cavities separated by the pillars and the contact shafts, sealing the accesses to the cavities with a third oxide layer, and introducing an inert ambiance while sealing the accesses to the cavities whereby the dielectric constant of the cavities surrounding the interconnect line is approximately that of the inert ambiance.

REFERENCES:
patent: 4987101 (1991-01-01), Kaanta et al.
patent: 5407860 (1995-04-01), Stoltz et al.
patent: 5444015 (1995-08-01), Aitken et al.
patent: 5670828 (1997-09-01), Cheung et al.

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