Method of forming local etch stop landing pads for simultaneous,

Details Method of forming local etch stop landing pads for simultaneous, Method of forming local etch stop landing pads for simultaneous,

1992-08-20

1993-11-02

Hearn, Brian E.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

437 47, 437 49, 437 52, 437 7, H01L 21306, H01L 21265

Patent

active

052580962

ABSTRACT:
The present invention introduces the use of "local" etch stop layers having highly selective etch characteristics vis-a-vis insulating layers into which the contact/vias are etched. Any kind of conducting material which possesses etch selectivity to an insulator such as oxide (i.e. doped polysilicon, tungsten, tungsten silicide, titanium, titanium silicide, titanium nitride and the like) may be used and the process flow described herein uses conductively doped polysilicon as an example to accomplish this task without the need to add any extra photo or mask step to a conventional dynamic random access memory (DRAM) process flow and with the addition of a minimal number of deposition and etch steps. During a first masking step to open a contact, a subsequent etch opens up the P-channel gate area to thin down the underlying oxide. Polysilicon is then deposited which is followed by formation of an oxide. During a second masking step the oxide is etched and the polysilicon is etched thereby patterning the polysilicon and creating exposed polysilicon sidewalls. Dielectric isolation is then provided for the polysilicon sidewalls. In a first embodiment nitride spacers are then formed from a blanket layer of nitride which also results in nitride fillers about the polysilicon sidewalls. In a second embodiment the polysilicon sidewalls are oxidized thereby eliminating the steps for deposition and formation of nitride spacers. Next an etch stop layer of conductively doped polysilicon is deposited and covered with oxide. A third mask step allows a following etch to open local landing pads around future buried contact locations as well as define P-channel transistor gates.

REFERENCES:
patent: 5026657 (1991-06-01), Lee et al.
patent: 5030585 (1991-07-01), Gonzalez et al.
patent: 5043298 (1991-08-01), Yamada et al.
patent: 5134085 (1992-07-01), Gilgen et al.
patent: 5145801 (1992-09-01), Chhabra
patent: 5174858 (1992-12-01), Yamamoto et al.

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