Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Patent
1998-10-01
2000-09-12
Elms, Richard
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
438597, H01L 213205, H01L 214763
Patent
active
061177571
ABSTRACT:
A method of forming landing pads for a bit line and a node contact is provided. First, a first dielectric layer is formed on a substrate having a transistor structure thereon. The first dielectric layer is defined and etched in a self-aligned process to form a contact opening to the substrate. A second dielectric layer is formed on the first dielectric layer and is etched back to form a spacer on the opening sidewall. Then, a conductive layer is formed on the first dielectric layer and fills the opening. A bit line is formed by partially removing the conductive layer through a photo-resist mask provided on the conductive layer, wherein the conductive layer filling the opening is left to form a landing pad.
REFERENCES:
patent: 4997970 (1991-03-01), Woo et al.
patent: 5705427 (1998-01-01), Chan et al.
patent: 5902132 (1999-05-01), Mitsuhashi
Lin Benjamin Szu-Min
Wang Chuan-Fu
Elms Richard
Huang Jiawei
United Microelectronics Corp
Wilson Christian D.
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