Method of forming interconnects

Details Method of forming interconnects Method of forming interconnects

2002-01-25

2003-07-01

Cuneo, Kamand (Department: 2829)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S689000, C438S706000, C438S712000, C438S713000, C438S714000, C438S724000

Reexamination Certificate

active

06586324

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the manufacture of semiconductor devices, more particularly to a method of forming interconnects to reduce the aspect ratio of an opening and improve gap fill capability during the subsequent deposition of an insulating layer.
2. Description of the Related Art
Current integrated circuit manufacturing processes typically use multiple levels of some form of metal interconnect to provide interconnections between various circuits on the integrated circuit. For instance, current manufacturing processes are known to use five levels of metal interconnects. The etching process to form the interconnect requires that precisely defined regions of metal be exposed to etchants in order to selectively remove material from those regions. The patterns that define the regions are typically created using lithographic processes. For instance, a layer of photoresist is spin-coated onto a substrate, and the resist layer is selectively exposed to a form of radiation, such as ultraviolet light, electrons, or x-rays.
An exposure tool and mask, or data tape in electron beam lithography, are used to effect the desired selective exposure. Openings in the resist corresponding to the selective exposure are formed in a subsequent development step. Next, an etching step is applied, and the regions of the substrate exposed by the openings are removed. The etching provides a desired pattern in the metal layer to form the final usable interconnect.
The process limitations are compounded by poor selectivity between metal such as aluminum, and photoresist during a typical metal etching process. As the photoresist becomes thicker, the openings near the bottom surface tend to narrow. As a result, thicker photoresist tends to limit the resolution. As the thickness of metal film is increased, thicker and thicker photoresist must be used in order to provide enough process margin during the etching step. That is, in order to prevent excessive metal erosion during the etching step, sufficient photoresist must be left over protected metal areas during the metal etch portion of the process. However, as resists become thicker, it becomes harder to resolve smaller features with an acceptable depth of focus.
Therefore, generally speaking, the resolution is improved by thinning the photoresist. That is, thinner resist allows the extension of standard exposure tools to finer geometries. However, the photoresist must remain thick enough to avoid metal being eroded by the etchant. For instance, for submicron patterns, the photoresist might be approximately 2 to 3 times as thick as an underlying metal layer in order to adequately protect the metal layer from an etchant that is particularly harsh to the photoresist. Unfortunately, at this thickness, the resolution of the photoresist may produce significant deviations between the desired pattern and the actual pattern transferred to the substrate.
Accordingly, there exists a need for an efficient method of patterning metal layers forming interconnects using a thin layer of photoresist while adequately protecting the metal film from the etching step. To meet the requirements, an oxide hard mask has been used to replace the thick photoresist on the aluminum layer, having an oxide layer thereunder, as the etching mask during etch of aluminum. However, the gap fill capability during the subsequent deposition of an insulating layer is insufficient because an aspect ratio of the opening between the stacked structures consisting of the etched aluminum interconnect and the remaining oxide mask becomes approximately 3 to 4.
SUMMARY OF THE INVENTION
In view of the above disadvantages, an object of the invention is to provide a method of forming interconnects to reduce the aspect ratio of an opening by the formation of a facet mask. As a result, the gap fill capability during the subsequent deposition of an insulating layer can be improved.
Accordingly, the above object is attained by providing a method of forming interconnects. It is suitable for a semiconductor substrate with a first insulating layer thereon. First, a metal layer is provided on the first insulating layer followed by the formation of a masking layer with patterns overlaying the metal layer. Second, the patterns of the masking layer are transferred into the metal layer so as to form an opening by an etching step.
Then, silicon nitride liner is conformally formed on the surfaces of the masking layer, the metal layer and the first insulating layer. Third, the silicon nitride liner and the masking layer are partially removed by reactive ion etching to leave a facet mask with high etch selectivity of the silicon nitride liner at the corner with respect to the bottom to reduce the aspect ratio of the opening. That is, the etching rate of the silicon nitride liner at the corner is higher than that at the bottom. Fourth, the remaining silicon nitride liner is removed to expose the first insulating layer. Then, a second insulating layer is deposited to fill the opening.
In an embodiment of the invention, the metal layer is preferably an aluminum layer, and the masking layer is composed of silicon oxide.
Moreover, in another embodiment of the invention, the silicon nitride liner and the masking layer are removed by reactive ion etching using the mixture gas of argon gas and carbon fluoride such as at least one CHF
3
, CH
3
F, CH
2
F
2
, CF
4
, C
4
F
6
, C
4
F
8
, or C
5
F
8
. Preferably, at least one oxygen-containing gas such as CO or O
2
is introduced into the mixture gas. Furthermore, in the method of forming interconnects, the silicon nitride liner and the masking layer are preferably removed at a pressure of about 3 mtorr to 100 mtorr with power of about 500 W to 2000 W.
The above object is also attained by providing a method of forming interconnects. It is suitable for a semiconductor substrate with a first silicon oxide layer thereon. First, a metal layer is provided on the first silicon oxide layer followed by the formation of a silicon oxide masking layer with patterns overlaying the metal layer. Second, the patterns of the silicon oxide masking layer are transferred into the metal layer so as to form an opening.
Third, a silicon nitride liner is conformally formed on the surfaces of the silicon oxide masking layer, the metal layer and the first silicon oxide layer. Fourth, the silicon nitride liner and the masking layer are partially removed by reactive ion etching to leave a facet mask, wherein the silicon nitride liner at the corner has an etch selectivity of 10 to 20 with respect to the silicon oxide masking layer, the silicon nitride liner at the bottom has an etch selectivity of about 50 with respect to the first silicon oxide layer to reduce the aspect ratio of the opening. Thereafter, the remaining silicon nitride liner is removed. Next, a second silicon oxide layer is deposited to fill the opening with a lower aspect ratio.


REFERENCES:
patent: 5534107 (1996-07-01), Gray et al.
patent: 6117345 (2000-09-01), Liu et al.
patent: 6177331 (2001-01-01), Koga
patent: 6225217 (2001-05-01), Usami et al.
patent: 6274498 (2001-08-01), Moore et al.
patent: 6281051 (2001-08-01), Tsutsumi

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