Method of forming interconnections

Details Method of forming interconnections Method of forming interconnections

1998-12-04

2001-01-30

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S624000, C438S622000, C438S637000, C257S758000, C257S760000, C257S637000, C257S639000, C257S640000

Reexamination Certificate

active

06180507

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Ser. No. 87117030, filed Oct. 14, 1998 the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a method of forming semiconductor integrated circuits (ICs), and more particularly to a method of forming interconnections.
2. Description of the Related Art
Increasing integration of an integrated circuit (IC) device results in insufficient wafer surface for formation of desired interconnects. In accordance with a need of interconnects in a metal-oxide semiconductor (MOS) transistor that has a highly reduced dimension, an interconnect structure is necessarily designed to include at least two metal layers. These multiple metal layers are usually insulated and held by inter-metal dielectric (IMD) layers in between them. According to designed circuit architecture, these metal layers have to be electrically coupled together at certain places. A via structure formed in the IMD layer is employed for this purpose of coupling. The via structure typically includes a via hole and a conductive via plug to fill the via hole. These two metal layers on both sides of the IMD layer are electrically coupled through the conductive via plug.
FIGS. 1A
to
1
E are schematic, cross-sectional views, illustrating a conventional fabrication process of a interconnection. In
FIG. 1A
, a substrate
100
having a device structure thereon is provided. A defined metal layer
102
as a metal line is formed on the substrate
100
.
In
FIG. 1B
, a dielectic layer
106
is formed on the substrate
100
and on the defined metal layer
102
. A planarization process is performed on the dielectric layer
106
to obtain a planar surface on the dielectric layer
106
. A material of the dielectric layer
106
is silicon oxide with a dielectric constant of about 4-4.9.
In
FIG. 1C
, the dielectric layer
106
is defined to form a via hole
108
in the dielectric layer
106
using the metal layer
102
as an etching stop layer. A conformal barrier/glue layer
107
is formed on the dielectric layer
106
.
In
FIG. 1D
, a conductive layer
110
is formed on the barrier/glue layer
107
. The barrier/glue layer
107
enhances the adhesion between the conductive layer
110
and the dielectric layer
106
. The conductive layer
110
fills the via hole
108
to form a metal plug electrically coupling with the metal layer
102
. A planarization process is performed to planarize the conductive layer
110
.
In
FIG. 1E
, the conductive layer
110
and the barrier/glue layer
107
are defined to form a wiring line
110
a
. An interconnection is thus completed.
The metal layer
102
, the dielectric layer
106
and the conductive layer
110
constitute a capacitor structure called “parasitic capacitor”. Since the dielectric constant of the dielectric layer
106
is high, problems with the parasitic capacitor become more serious than before when the feature size is smaller and a distance between two metal lines is shorter than before. One of the problems is RC delay. Another of the problems is cross-talk between the metal lines. These problems decrease the performance of devices.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a method of forming interconnections to form a dielectric layer with a low dielectric constant. RC delay is thus reduced to enhance the operated rate of the devices. Cross-talk between metal lines is also prevented to enhance the quality of the devices.
The invention achieves the above-identified objects by providing a method of forming interconnections. A substrate is provided. A defined metal layer is formed as a metal line on the substrate. An oxide layer is formed on the metal layer and on the substrate. A silicon nitride layer is formed on the oxide layer. The oxide layer and the silicon nitride layer constitute a seed layer. A via hole is formed in the silicon nitride layer to expose the oxide layer positioned over the metal layer. A dielectric layer is formed on the seed layer. Since the silicon nitride layer and the oxide layer are different, a part of the dielectric layer positioned on the silicon nitride layer is a silicon oxide layer having holes therein. The other dielectric layer positioned on the oxide layer within the via holes is a dense silicon oxide layer.


REFERENCES:
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patent: 5461003 (1995-10-01), Havemann et al.
patent: 5470802 (1995-11-01), Gnade et al.
patent: 5472913 (1995-12-01), Havemann et al.
patent: 5482894 (1996-01-01), Havemann
patent: 5488015 (1996-01-01), Havemann et al.
patent: 5494858 (1996-02-01), Gnade et al.
patent: 5650360 (1997-07-01), Tomita

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