Method of forming interconnect

Details Method of forming interconnect Method of forming interconnect

2001-01-04

2002-12-17

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S622000, C438S637000, C438S700000

Reexamination Certificate

active

06495451

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a method of forming a metal interconnect with good electrical characteristics by a dual damascene process just as intended.
Hereinafter, a known interconnect forming method will be described with reference to
FIGS. 5A through 5F
.
FIGS. 5A through 5F
illustrate cross-sectional structures corresponding to respective process steps for forming interconnects by a known dual damascene process.
First, as shown in
FIG. 5A
, a first insulating film
102
is deposited on an insulating substrate
101
, and a first trench pattern is formed out of the first insulating film
102
. Next, the first trench pattern is filled in with a first metallization material
104
(e.g., copper (Cu)) with a first barrier film
103
interposed therebetween and the material
104
and film
103
filled in are planarized. In this manner, a first metal interconnect
105
is formed out of the first barrier film
103
and first metallization material
104
. Subsequently, a second insulating film
106
of silicon nitride, for example, is deposited, as a passivation film for the first metallization material
104
, over the first insulating film
102
and first metal interconnect
105
. Then, an interlevel dielectric film
107
of silicon dioxide, for example, is deposited on the second insulating film
106
.
Next, as shown in
FIG. 5B
, through holes
107
a
are opened by removing respective parts of the interlevel dielectric film
107
that are located over the first metal interconnect
105
.
Then, as shown in
FIG. 5C
, a positive resist pattern
108
, which will be used for defining a second trench pattern and which has openings over the holes
107
a
, is defined on the interlevel dielectric film
107
. Each of the openings of the resist pattern
108
has a diameter equal to or greater than that of an associated one of the holes
107
a
of the interlevel dielectric film
107
. At this point of the process, if the holes
107
a
, i.e., the openings of the resist pattern
108
, have their diameter reduced to a certain size to meet requirements of miniaturization, then the resist material
108
a
, filled in the holes
107
a
, cannot be exposed to radiation sufficiently in a subsequent exposure process for the resist pattern
108
. This is because the smaller the diameter of the holes
107
a
or openings, the harder it is for the exposing radiation to reach the deeper levels in the holes
107
a
. As a result, part of the resist material
108
a
is unintentionally left inside the holes
107
a
. The remaining part of the resist material
108
a
is likely to reach a level higher than the bottom of a second trench pattern that will be defined in the interlevel dielectric film
107
in the next process. According to another method, a resist material may also be intentionally filled in the holes
107
a
to minimize damage done on the first metal interconnect
105
when the second trench pattern is defined. However, just like the resist material
108
a
shown in FIG. SC, the same unwanted results are also obtained even by that alternative method.
Next, as shown in
FIG. 5D
, the interlevel dielectric film
107
is etched using the resist pattern
108
as a mask, thereby forming the second trench pattern
107
b
, which is linked to the holes
107
a
, in the interlevel dielectric film
107
. Thereafter, the resist pattern
108
and resist material
108
a
are removed. In this case, an etching residue
110
of the resist material
108
a
, which has been filled in the holes
107
a
, is left inside the second trench pattern
107
b
. The residue
110
has insulation properties.
Then, as shown in FIG. SE, a second barrier film
111
is deposited over the holes
107
a
and second trench pattern
107
b
, which have been formed in the interlevel dielectric film
107
. Thereafter, these holes
107
a
and pattern
107
b
are filled in with a second metallization material
112
such as Cu.
Subsequently, as shown in
FIG. 5F
, unnecessary portions of the second barrier film
111
and second metallization material
112
are removed, thereby forming second metal interconnects
113
out of the second barrier film
111
and second metallization material
112
.
According to this known method, however, the insulating etching residue
110
, called an “inner crown”, is left inside the second trench pattern
107
b
in the interlevel dielectric film
107
as shown in FIG.
5
D. Thus, the second metal interconnects
113
have their resistance increased or might even be disconnected from the first metal interconnect
105
in a worst-case scenario.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to avoid the unwanted increase in resistance or disconnection of metal interconnects that is usually caused by the etching residue in a known dual damascene process.
The present inventors conducted intensive research on exactly how the “inner crown” appeared where a groove-like trench pattern was formed in the upper part of an insulating film so as to be filled with a metallization material in a subsequent process. As a result, we found that the insulating etching residue extended from a stepped interface between a resist material, with which through holes to be linked to the trench pattern had been filled in, and the insulating film.
Thus, we concluded that if the resist material, filled in the exposed through holes to define a resist pattern for the trench pattern to be formed later, is allowed to reach a level no higher than the bottom of the trench pattern, then the inner crown can be eliminated.
To achieve the above object, an inventive interconnect forming method includes the steps of: a) forming a through hole in an insulating film over a substrate; b) depositing a photosensitive masking material over the insulating film as well as inside the through hole; c) patterning the masking material, thereby forming a mask pattern, which has an opening located over the through hole and is used to define a trench; d) etching the insulating film to a predetermined depth using the mask pattern, thereby defining a trench pattern, which is linked to the through hole, in an upper part of the insulating film; e) filling in the through hole and the trench pattern with a conductive material; and f) defining the mask pattern so that no remaining part of the masking material, which has been filled in the through hole, will reach a level higher than the bottom of the trench pattern. The step f) is performed before the step d).
According to the inventive method, before the trench pattern is formed, the mask pattern, used to form the trench, is defined so that no remaining part of the masking material, which has been filled in the through hole, will reach a level higher than the bottom of the trench pattern. Thus, no etching residue of the masking material is left in the upper part of the through hole. And it is possible to prevent the etching residue from increasing the resistance of the metal interconnects or disconnecting the interconnects from each other. As a result, highly reliable metal interconnects with good electrical characteristics can be obtained.
In one embodiment of the present invention, the masking material may be exposed in the step c) to radiation at such a dose as needed for the radiation to pass through the masking material on the insulating film and then the exposed masking material may be developed, thereby forming the mask pattern out of the masking material.
In another embodiment of the present invention, the step d) may include the step of rounding a corner between the top of the through hole and the bottom of the trench pattern in the insulating film.
In still another embodiment, the step f) may include the steps of: i) depositing a negative resist as the masking material on the insulating film in the step b); and ii) leaving part of the negative resist, which has been filled in the through hole, unexposed and then developing and removing the unexposed part of the negative resist in the step c).
In yet another embodiment, the step f) may include the steps

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