Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2005-05-24
2005-05-24
Blum, David S. (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S714000
Reexamination Certificate
active
06897120
ABSTRACT:
A method of forming integrated circuitry includes forming a silicon nitride comprising layer over a semiconductor substrate. At least a portion of the silicon nitride comprising layer is etched using an etching chemistry comprising ammonia and at least one fluorocarbon. A method of forming shallow trench isolation in a semiconductor substrate includes depositing a silicon nitride comprising layer over a bulk semiconductor substrate. A photoresist comprising masking layer is formed over the silicon nitride comprising layer. The photoresist comprising masking layer is patterned effective to form a plurality of shallow trench mask openings therethrough. The silicon nitride comprising layer is etched through the mask openings substantially selectively relative to the photoresist using an etching chemistry comprising ammonia and at least one fluorocarbon.
REFERENCES:
patent: 3990927 (1976-11-01), Montier
patent: 4352724 (1982-10-01), Sugishima et al.
patent: 4474975 (1984-10-01), Clemons et al.
patent: 4836887 (1989-06-01), Daubenspeck et al.
patent: 4985373 (1991-01-01), Levinstein et al.
patent: 5156881 (1992-10-01), Okano et al.
patent: 5182221 (1993-01-01), Sato
patent: 5286344 (1994-02-01), Blalock et al.
patent: 5410176 (1995-04-01), Liou et al.
patent: 5470798 (1995-11-01), Ouellet
patent: 5719085 (1998-02-01), Moon et al.
patent: 5741740 (1998-04-01), Jang et al.
patent: 5776557 (1998-07-01), Okano et al.
patent: 5786039 (1998-07-01), Brouquet
patent: 5801083 (1998-09-01), Yu et al.
patent: 5814563 (1998-09-01), Ding et al.
patent: 5863827 (1999-01-01), Joyner
patent: 5883006 (1999-03-01), Iba
patent: 5888880 (1999-03-01), Gardner et al.
patent: 5895253 (1999-04-01), Akram
patent: 5904540 (1999-05-01), Sheng et al.
patent: 5930645 (1999-07-01), Lyons et al.
patent: 5943585 (1999-08-01), May et al.
patent: 5950094 (1999-09-01), Lin et al.
patent: 5960299 (1999-09-01), Yew et al.
patent: 5972773 (1999-10-01), Liu et al.
patent: 5989987 (1999-11-01), Kuo
patent: 5998280 (1999-12-01), Bergemont et al.
patent: 6030881 (2000-02-01), Papasouliotis et al.
patent: 6051477 (2000-04-01), Nam
patent: 6103137 (2000-08-01), Park
patent: 6140168 (2000-10-01), Tan et al.
patent: 6156674 (2000-12-01), Li et al.
patent: 6300219 (2001-10-01), Doan et al.
patent: 9-129608 (1997-05-01), None
patent: 2000349071 (2000-12-01), None
Stanley Wolf Silicon Processing for the VLSI Era vol. 2 Lattice Press 1990 pp. 52-54.*
Bell Labs Scientists Develop 193 nm Single-Layer Photoresist Bell Labs News Apr. 1997.*
Stanley Wolf Silicon Processing for the VSLI Era vol. 1 Lattice Press 1986 pp. 551-557.*
U.S. Appl. No. 09/752,685, filed Jan. 3, 2001, Trapp.
Beekmann et al.,Sub-micron Gap Fill and In-Situ Planarisation Using Flowfill™ Technology, Electrotech, Presented at ULSI Conference, Portland, Oregon (Oct. 1995).
Horie et al.,Kinetics and Methanism of the Reactions of O(3P)With SiH4, CH3SiH3, (CH3)2SiH2, and(CH3)3SiH, 95 J. Phys. Chem. No. 95, pp. 4393-4400 (1991).
Joshi et al.,Plasma Deposited Organosilicon Hydride Network Polymers as Versatile Resists for Entirely Dry Mid-Deep UV Photolithography, 1925 SPIE 709-720 (1993).
Kiermasz et al.,Planarization for Sub-Micron Devices Utilising a New Chemistry, Electrotech, Presented at DUMIC Conference, California (Feb. 1995).
Matsuura et al.,A Highly Reliable Self-planarizing Low-k Intermetal Dielectric for Sub-quarter Micron Interconnects, IEEE 785-788 (1997).
Matsuura et al.,Novel Self-planarizing CVD Oxide for Interlayer Dielectric Applications, IEEE 117-120 (1994).
McClatchie et al.,Low Dielectric Constant Flowfill® Technology for IMD Applications, 7 pages (pre-Aug. 1993).
Withnall et al.,Matrix Reactions of Methylsilanes and Oxygen Atoms, 92 J. Phys. Chem., No. 3, pp. 594-602 (1988).
Smolinsky et al.,Reactive Ion Etching of Silicon Oxides with ammonia and Trifluoromethane. The Role of . . ., J. Electrochem. Soc.: Solid-State Science and Technology, pp. 1036-1039 (May 1982).
Blum David S.
Micro)n Technology, Inc.
Wells St. John P.S.
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