Semiconductor device manufacturing: process – Chemical etching – Altering etchability of substrate region by compositional or...
Reexamination Certificate
2001-08-07
2004-10-19
Norton, Nadine G. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Altering etchability of substrate region by compositional or...
C438S706000, C438S714000, C438S723000, C438S724000
Reexamination Certificate
active
06806197
ABSTRACT:
TECHNICAL FIELD
This invention relates to methods of forming integrated circuitry, to methods of forming contact openings, and to integrated circuitry.
BACKGROUND OF THE INVENTION
Semiconductor processing often involves the deposition of films or layers over or on a semiconductor substrate surface which may or may not have other layers already formed thereon. In typical circuitry fabrication, portions of an outer layer are masked, typically using photoresist, to provide a desired pattern over the outer layer. An underlying layer is then removed by chemical etching through the mask opening, with the mask covering and protecting other areas from the etching. Often it is desirable to etch an outer layer or layers selectively relative to an underlying layer. Accordingly, materials on the substrate, etch chemistry and conditions are continually being developed and improved to achieve a manner by which the desired layer(s) can be etched while stopping and substantially not etching an underlying layer.
Also, some layers are removed by mechanical polishing action or by chemical mechanical polishing action. In many such instances, it is also desirable to remove one or more layers while stopping on some immediately underlying layer.
SUMMARY
The invention includes methods of forming integrated circuitry, methods of forming contact openings, and integrated circuitry. In one implementation, a silicon nitride comprising layer is formed over a semiconductor substrate. The silicon nitride comprising layer includes Al, Ga or a mixture thereof. A silicon dioxide comprising layer is formed proximate the silicon nitride comprising layer. The silicon dioxide comprising layer is removed substantially selectively relative to the silicon nitride comprising layer, with the Al, Ga or a mixture thereof enhancing selectivity to the silicon nitride comprising layer during the removal.
In one implementation, a substantially undoped silicon dioxide comprising layer is formed over a semiconductor substrate. The substantially undoped silicon dioxide comprising layer includes B, Al, Ga or mixtures thereof. A doped silicon dioxide comprising layer is formed proximate the substantially undoped silicon dioxide comprising layer. The doped silicon dioxide comprising layer is removed substantially selectively relative to the substantially undoped silicon dioxide comprising layer, with the B, Al, Ga or mixtures thereof enhancing selectivity to the substantially undoped silicon dioxide comprising layer during the removal.
In one implementation, integrated circuitry includes a pair of spaced conductive device components received over a substrate, with such at least partially defining a node location there between. Each device component has at least one sidewall which faces the other device component of the pair. An insulative material mass is received over each of the sidewalls. The masses are laterally spaced from one another in a non-contacting relationship. The masses comprise a first insulative material comprising B, Al, Ga or mixtures thereof. A conductive contact is received between the insulative material masses in electrical connection with the node location.
REFERENCES:
patent: 4514251 (1985-04-01), van Ommen et al.
patent: 4780426 (1988-10-01), Koshino et al.
patent: 4843034 (1989-06-01), Herndon et al.
patent: 5087589 (1992-02-01), Chapman et al.
patent: 5436186 (1995-07-01), Hsue et al.
patent: 5780338 (1998-07-01), Jeng et al.
patent: 5792689 (1998-08-01), Yang et al.
patent: 6063548 (2000-05-01), Chu et al.
patent: 6066550 (2000-05-01), Wang
patent: 6194265 (2001-02-01), Chang et al.
Lawlor Brian F.
Trapp Shane J.
Norton Nadine G.
Tran Binh X
Wells St. John P.S.
LandOfFree
Method of forming integrated circuitry, and method of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming integrated circuitry, and method of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming integrated circuitry, and method of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3324355