Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2000-09-14
2004-10-05
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S771000, C438S788000, C438S791000
Reexamination Certificate
active
06800512
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of forming an insulating film in which a highly reliable oxide film can be formed at a low temperature and a method of fabricating a semiconductor device by utilizing the method of forming an insulating film.
In accordance with recent demands for high integration of semiconductor integrated circuits, for example, a very shallow junction structure is employed in forming a transistor and an STI (shallow trench isolation) structure is employed in forming an isolation. Since the very shallow junction structure and the STI are thus employed, dislocation defects are caused in an active region due to stress collected on the edge of the STI during formation of a gate oxide film (by thermal oxidation). As a result, junction leakage can be increased, or variation in the threshold voltage can be increased owing to change of junction profile caused in the formation of the gate oxide film. Therefore, in order to overcome these problems, it is very significant to conduct the process for forming an oxide film at a low temperature.
Also, in accordance with the demands for high integration of semiconductor integrated circuits, the gate length of a MOSFET is reduced, which makes it difficult to suppress the short channel effect. Therefore, the short channel effect is suppressed by employing a gate electrode structure designated as a dual gate electrode obtained by implanting phosphorus ions into a polysilicon film for a gate electrode of an NMOSFET and implanting boron ions into a polysilicon film for a gate electrode of a PMOSFET.
FIGS.
21
(
a
) through
21
(
d
) and
22
(
a
) through
22
(
d
) are sectional views for showing procedures in fabrication of a conventional CMOS device having a trench isolation structure and a dual gate electrode structure.
First, in the procedure shown in FIG.
21
(
a
), a trench isolation region
101
is formed in a Si substrate
100
, and then, a photoresist film
103
covering an NMOSFET formation region Rn and having an opening on a PMOSFET formation region Rp is formed on a protection oxide film
102
by photolithography. Thereafter, phosphorus ions (P
+
) for forming an N-type well region
104
, phosphorus ions (P
+
) for controlling a threshold voltage and arsenic ions (As
+
) for stopping punch-through are implanted into a region of the Si substrate
100
within the opening of the photoresist film
103
(namely, the PMOSFET formation region Rp).
Then, in the procedure shown in FIG.
21
(
b
), the photoresist film
103
is removed by ashing and RCA cleaning.
Next, in the procedure shown in FIG.
21
(
c
), a photoresist film
105
covering the PMOSFET formation region Rp and having an opening on the NMOSFET formation region Rz is formed on the protection oxide film
102
by the photolithography. Thereafter, boron ions (B
+
) for forming a P-type well region
106
, boron ions (B
+
) for controlling a threshold voltage and boron ions (B
+
) for stopping punch-through are implanted into a region of the Si substrate
100
within the opening of the photoresist film
105
(namely, the NMOSFET formation region Rn).
Then, in the procedure shown in FIG.
21
(
d
), the photoresist film
105
is removed by the ashing and the RCA cleaning, and the protection oxide film
102
is also removed. Thereafter, the Si substrate
100
is heated at approximately 800 through 1000° C. in an oxygen atmosphere, thereby forming gate oxide films
107
a
and
107
b
on the N-type well region
104
and the P-type well region
106
, respectively.
Subsequently, in the procedure shown in FIG.
22
(
a
), after depositing a polysilicon film
108
for a gate electrode on the substrate, a photoresist film
109
covering the NMOSFET formation region Rn and having an opening on the PMOSFET formation region Rp is formed on the polysilicon film
108
. Thereafter, boron ions (B
+
) are implanted into a region of the polysilicon film within the opening of the photoresist film
109
(namely, the PMOSFET formation region Rp).
Similarly, in the procedure shown in FIG.
22
(
b
), after removing the photoresist film
109
by the ashing and the RCA cleaning, a photoresist film
110
covering the PMOSFET formation region Rp and having an opening on the NMOSFET formation region Rn is formed on the polysilicon film
108
by the photolithography. Thereafter, phosphorus ions (P
+
) are implanted into a region of the polysilicon film
108
within the opening of the photoresist film
110
(namely, the NMOSFET formation region Rn).
Next, in the procedure shown in FIG.
22
(
c
), the photoresist film
110
is removed by the ashing and the RCA cleaning, and then, a heat treatment is carried out for activating the impurities implanted into the polysilicon film
108
. In this manner, a P-type polysilicon film
108
p
is formed in the PMOSFET formation region Rp and an N-type polysilicon film
108
n
is formed in the NMOSFET formation region Rn.
Then, the P-type polysilicon film
108
p
and the N-type polysilicon film
108
n
are respectively patterned into a gate electrode
108
a
of the PMOSFET and a gate electrode
108
b
of the NMOSFET.
Furthermore, in order to cope with reduction in a chip area and high operation speed of a device, the resistance of the gate electrode of a MOSFET has recently been lowered. As one of promising means for lowering the resistance, the so-called polymetal gate structure or polycide gate structure in which part of the gate electrode is formed from a metal (refractory metal or its silicide) is known.
FIGS.
23
(
a
) through
23
(
d
) are sectional views for showing procedures in fabrication of a conventional CMOS device having the polymetal structure.
First, through the same procedures as those shown in FIGS.
21
(
a
) through
21
(
d
), a trench isolation region
101
for isolating a PMOSFET formation region Rp and an NMOSFET formation region Rn from each other, an N-type well region
104
, a P-type well region
106
and gate oxide films
107
a
and
107
b
are formed in a Si substrate
100
. Thereafter, as is shown in FIG.
23
(
a
), a polysilicon film
120
, a metal film
121
of titanium silicide or the like and an insulating film
122
of a silicon nitride film or the like are successively deposited on the substrate.
Next, in the procedure shown in FIG.
23
(
b
), a photoresist film
115
covering a gate electrode formation region is formed by the photolithography, and then, dry etching (anisotropic etching) is carried out by using the photoresist film as a mask, thereby patterning the insulating film
122
, the metal film
121
and the polysilicon film
120
. In this manner, a gate electrode
125
a
including a bottom gate electrode
120
a
and a top gate electrode
121
a
, and an over-gate protection film
122
a
are formed in the PMOSFET formation region Rp. Also, a gate electrode
125
b
including a bottom gate electrode
120
b
and a top gate electrode
121
b
, and an over-gate protection film
122
b
are formed in the NMOSFET formation region Rn.
Then, in the procedure shown in FIG.
23
(
c
), a photoresist film
116
covering the NMOSFET formation region Rn and having an opening on the PMOSFET formation region Rp is formed on the substrate. Thereafter, boron ions (B
−
) are implanted into the Si substrate
100
by using the photoresist film
116
and the gate electrode
125
a
as masks, thereby forming source/drain regions
126
of the PMOSFET.
Next, in the procedure shown in FIG.
23
(
d
), the photoresist film
116
is removed by the ashing and the RCA cleaning, and then, a photoresist film (not shown) covering the PMOSFET formation region Rp and having an opening on the NMOSFET formation region Rn is formed on the substrate. Thereafter, arsenic ions (As
+
) are implanted into the Si substrate
100
by using the photoresist film and the gate electrode
125
b
as masks, thereby forming, source/drain regions
127
of the NMOSFET. Then, the photoresist film is removed by the ashing and the RCA cleaning.
The conventional semiconductor devices fabricated as de
Harada Yoshinao
Itonaga Kazuichiro
Miyanaga Isao
Nakaoka Hiroaki
Yamamoto Akihiro
Brewster William M.
Coleman W. David
Nixon & Peabody LLP
Studebaker Donald R.
LandOfFree
Method of forming insulating film and method of fabricating... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming insulating film and method of fabricating..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming insulating film and method of fabricating... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3288576