Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-03-26
2004-08-31
Gurley, Lynne (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S624000, C438S637000, C438S638000, C438S687000, C438S780000, C438S781000, C438S782000, C438S787000, C438S788000, C438S789000, C438S790000
Reexamination Certificate
active
06784092
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming an insulating film and a method of manufacturing a semiconductor device, particularly, to a method of manufacturing an interlayer insulating film having a low dielectric constant and a method of manufacturing a semiconductor device comprising the particular interlayer insulating film.
2. Description of the Related Art
In previous years, wiring layer included in a semiconductor device was mainly a single layer structure. However, a multi-layered wiring structure has come to be widely used in recent years in accordance with progress in the miniaturization and operating speed of semiconductor devices. As a matter of fact, semiconductor devices having metal wiring structures including as many as five or more layers have been developed and manufactured. However, a delay in the signal transmission, caused by a so-called “parasitic capacitance between the adjacent wiring layers” and the wiring resistance, has become prominent as a serious problem impeding progress in miniaturization of semiconductor devices. More specifically, the problem is growing, in that the delay in the signal transmission caused by the increase in the number of layers included in the multi-layered wiring structure impairs the increase in operating speed of the semiconductor device.
To date, various measures have been taken in order to avoid the delay in the signal transmission caused by use of-the multi-layered wiring structure. In general, delay in the signal transmission can be represented by the product of the parasitic capacitance between the adjacent wiring layers, noted above, and the wiring resistance. In order to improve delay in the signal transmission, it is desirable to decrease the parasitic capacitance between the adjacent wiring layers, and the wiring resistance.
For decreasing the wiring resistance, changes in the main component of the wiring material to a material having a lower resistivity have been attempted. For example, changing from conventional aluminum wiring to copper wiring has been attempted. However, it is difficult to process a copper layer into the shape of a wiring by dry etching as used in the preparation of conventional aluminum wiring. Therefore, when using copper for forming a wiring, a buried wiring structure is employed.
Also, in order to decrease the parasitic capacitance between the adjacent wiring layers, it has been attempted to form an insulating film by CVD, containing SiOF as a main component, in place of the conventional method of forming an insulating film containing SiO
2
as the main component. It has also been attempted to form a so-called “SOG” (Spin on Glass) film having a relative dielectric constant lower than that of a SiO
2
insulating film, or an insulating film having a low dielectric constant such as an organic resin film formed by a spin coating method.
In general, the lower limit of the relative dielectric constant of the SiO
2
film used widely in the past is said to be about 3.9. On the other hand, it may be possible to lower the relative dielectric constant of the SiOF film to about 3.3, although it is very difficult, in terms of the stability of the film, to lower the relative dielectric constant of the SiOF insulating film to a level lower than 3.3. On the other hand, it may be possible to lower the relative dielectric constant of the SOG film or the insulating film having a low dielectric constant, such as an organic resin film, to about 2.0. Such being the situation, the development of the technology for forming these films is being vigorously pursued.
However, low dielectric constant insulating films are also low density, and are brittle, leading to low mechanical strength films. To be more specific, an oxide film formed by the conventional CVD method has a modulus of elasticity of about 70 GPa. On the other hand, the modulus of elasticity of the insulating film having a low dielectric constant, i.e., the insulating film having a relative dielectric constant not higher than 3.0, is markedly lowered to 6 GPa or less. It follows that it is very difficult to use an insulating film having a low dielectric constant in large regions of a semiconductor device as a low dielectric constant interlayer insulating film, which is included in a multi-layered wiring structure having five or more layers and used in a high performance semiconductor device.
BRIEF SUMMARY OF THE INVENTION
A method for forming an insulating layer according to one embodiment of the present invention comprises:
coating a substrate with an insulating film material to form a coated film, the insulating film material containing at least first and second polymers differing from each other in average molecular weight; and
heating the coated film while irradiating the coated film with an electron beam.
A method for manufacturing a semiconductor device according to another embodiment of the present invention comprises:
coating a semiconductor substrate having an element formed therein with an insulating film material to form a coated film, the insulating film material containing at least first and second polymers differing from each other in average molecular weight; and
heating the coated film while irradiating the coated film with an electron beam to form an insulating film having a low dielectric constant.
REFERENCES:
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patent: 6093636 (2000-07-01), Carter et al.
patent: 6287955 (2001-09-01), Wang et al.
patent: 6498399 (2002-12-01), Chung et al.
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patent: 2002/0123240 (2002-09-01), Gallagher et al.
patent: 11-506872 (1999-06-01), None
Kurosawa, T., et al., “Composition For Film, Method of Film Formation, and Insulating Film”, U.S. Application Ser. No.: 09/670,547, filed on Sep. 27, 2000.
Shimada, M., et al., “Method of Manufacturing Semiconductor Device”, U.S. Application Ser. No. 09/985,003, filed on Oct. 19,2001.
Miyajima Hideshi
Nakata Rempei
Shimada Miyoko
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Gurley Lynne
Kabushiki Kaisha Toshiba
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