Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Patent
1997-12-17
2000-02-15
Hiteshew, Felisa
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
438722, H01L 21302
Patent
active
060252758
ABSTRACT:
A thick plated interconnect (80) may be fabricated by forming a metal layer (20) above a semiconductor layer (12). A dielectric layer (22) may be formed on the metal layer (20). A via (24) may be formed in the dielectric layer (22) to expose the metal layer (20). A copper lead (50) may be formed electrically coupled to the metal layer (20) through the via (24) of the dielectric layer (22). A barrier member (88) may be formed on the copper lead (50). A bondable member (86) comprising aluminum may be formed on the barrier member (88).
REFERENCES:
patent: 5238874 (1993-08-01), Yamada
patent: 5316974 (1994-05-01), Crank
patent: 5527739 (1996-06-01), Parrillo et al.
patent: 5674787 (1997-10-01), Zhao et al.
Efland Taylor R.
Keller Stephen A.
Mai Quang X.
Williams Charles E.
Brady III W. James
Donaldson Richard L.
Hiteshew Felisa
Okoro Bernadine
Texas Instruments Incorporated
LandOfFree
Method of forming improved thick plated copper interconnect and does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming improved thick plated copper interconnect and , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming improved thick plated copper interconnect and will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1905635