Method of forming holes in semiconductor integrated circuit devi

Details Method of forming holes in semiconductor integrated circuit devi Method of forming holes in semiconductor integrated circuit devi

1988-04-13

1989-08-15

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156643, 156646, 156651, 156653, 156657, 1566591, 20419237, 437198, 437199, 437203, 437238, B44C 122, C03C 1500, C03C 2506

Patent

active

048571415

ABSTRACT:
A recess is formed in the surface area of a layer-insulation film by an isotropic etching process, and a hole is formed in the recess by a first anisotropic etching process. After this, a second anisotropic etching process is effected to taper the hole to remove an edge portion at the opening of the recess, the boundary portion between the recess and the side wall formed by the anisotropic etching process, and the vertical side wall of the hole. A wiring metal layer is formed on part of the layer-insulation film and in the hole.

REFERENCES:
patent: 4461672 (1984-07-01), Musser
patent: 4484979 (1984-11-01), Stocker
patent: 4487652 (1984-12-01), Almgren
patent: 4495220 (1985-01-01), Wolf et al.
patent: 4522681 (1985-06-01), Gorowitz et al.
patent: 4560436 (1985-12-01), Bukhman et al.
patent: 4645562 (1987-02-01), Liao et al.
patent: 4705597 (1987-11-01), Gimpelson et al.
patent: 4764249 (1988-08-01), Gobrecht et al.

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