Method of forming hermetic wafer scale integrated circuit...

Details Method of forming hermetic wafer scale integrated circuit... Method of forming hermetic wafer scale integrated circuit...

2007-04-17

2007-04-17

Whitehead, Jr., Carl (Department: 2813)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Insulative housing or support

C257SE23009

Reexamination Certificate

active

11250821

ABSTRACT:
A wafer scale semiconductor integrated circuit packaging technique provides a hermetic seal for the individual integrated circuit die formed as part of the wafer scale structure. A semiconductor wafer is manufactured to include a number of individual semiconductor die. Each individual die formed on the wafer includes a number of bond pads that are exposed on the die surface in various locations to provide electrical connections to the circuitry created on the die. The wafer further includes a planar glass sheet that is substantially the same size as the wafer, the glass sheet being adhered to the wafer using a suitable adhesive. The glass sheet has a number of pre-formed holes in it, the arrangement of the pre-formed holes corresponding to the location of the bond pads at each of the individual semiconductor die formed as part of the wafer structure. Following adherence of the glass sheet to the semiconductor wafer utilizing the intermediate adhesive material, metal connections are made between pads formed on the glass sheet and the bond pads formed on the integrated circuit die. Solder balls are then attached to the pads on the glass sheet to provide a conductive flow between the solder balls and the bond pads. After the solder balls are attached, trenches are cut around each of the individual die on the wafer. The trenches are cut at an angle and extend through the glass sheet and the intermediate adhesive material and into the semiconductor substrate in which the integrated circuits are formed. After the trenches are cut around each individual semiconductor die, a noble metal is deposited on the sidewalls of the trench to extend over the interface between the glass sheet, the adhesive material and the semiconductor die. The wafer is then cut along the noble metal lined trenches to provide individual, hermetically sealed packaged integrated circuit die.

REFERENCES:
patent: 4356374 (1982-10-01), Noyori et al.
patent: 5258648 (1993-11-01), Lin
patent: 5705858 (1998-01-01), Tsukamoto
patent: 5814894 (1998-09-01), Igarashi et al.
patent: 5844304 (1998-12-01), Kata et al.
patent: 6149122 (2000-11-01), Berger et al.
patent: 6221751 (2001-04-01), Chen et al.
patent: 6300235 (2001-10-01), Feldner et al.
patent: 6303977 (2001-10-01), Schroen et al.
patent: 6607941 (2003-08-01), Prabhu et al.
patent: 2002/0100608 (2002-08-01), Fushie et al.
patent: 2002/0192939 (2002-12-01), Sugihara

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