Method of forming hemispherical grain polysilicon over lower ele

Details Method of forming hemispherical grain polysilicon over lower ele Method of forming hemispherical grain polysilicon over lower ele

1998-11-13

2000-09-19

Whitehead, Jr., Carl

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

438398, 438253, 438255, H01L 2120

Patent

active

061211095

ABSTRACT:
A method of forming a layer of hemispherical grain polysilicon over the lower electrode of a capacitor. The method comprises the steps of providing a substrate that has a field effect transistor already formed thereon, and then forming an insulating layer with a contact opening over the substrate. Subsequently, a polysilicon layer is formed over the insulating layer that completely fills the contact opening. This polysilicon layer is electrically coupled to one of the source/drain regions of the field effect transistor. Thereafter, a thin buffer layer is formed over the polysilicon layer, and then the thin buffer layer is patterned. The thin buffer layer is used as a mask for covering the polysilicon layer that is to be part of the lower electrode of a capacitor. Next, a plasma etching operation is carried out to remove the thin buffer layer and a portion of the polysilicon layer at the same time. Finally, a heat treatment is carried out to form a hemispherical grain polysilicon layer over the surface of the lower electrode.

REFERENCES:
patent: 5227322 (1993-07-01), Ko et al.
patent: 5340765 (1994-08-01), Dennison et al.
patent: 5837581 (1998-11-01), Cheng
patent: 5858835 (1999-01-01), Lin
patent: 5858838 (1999-01-01), Wang et al.
patent: 5874336 (1999-02-01), Cherng
patent: 6022775 (2000-02-01), Tsai et al.

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