Method of forming graded thin films using alternating pulses...

Details Method of forming graded thin films using alternating pulses... Method of forming graded thin films using alternating pulses...

2001-03-06

2003-03-18

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S643000, C438S653000, C438S674000, C438S678000, C438S687000, C438S783000, C438S784000, C438S785000, C438S787000

Reexamination Certificate

active

06534395

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to forming layers in integrated circuits, and more particularly to depositing thin films with graded impurity concentrations.
BACKGROUND OF THE INVENTION
There are numerous semiconductor process steps involved in the development of modem day integrated circuits (ICs). From the initial fabrication of silicon substrates to final packaging and testing, integrated circuit manufacturing involves many fabrication steps, including photolithography, doping, etching and thin film deposition. As a result of these processes, integrated circuits are formed of microscopic devices and wiring amid multiple layers.
A basic building block of the integrated circuit is the thin film transistor (TFT). The transistor includes a gate dielectric layer sandwiched between a “metal” layer and the semiconductor substrate, thus the acronym “MOS” for metal-oxide-semiconductor. In reality, the gate electrode is typically formed of conductively doped silicon rather than metal. The gate dielectric most commonly employed is SiO
2
or silicon dioxide.
Today's market demands more powerful and faster integrated circuits. In pursuit of such speed and lower power consumption, device packing densities are continually being increased by scaling down device dimensions. To date, this scaling has reduced gate electrode widths to less than 0.25 &mgr;m. Currently, commercial products are available employing gate widths or critical dimensions of 0.18 &mgr;m or less. The scaling rules that apply to these small devices call for very thin gate oxide layers, which have grown smaller with each generation of MOS integrated circuits. The thickness of gate oxides is made as small as possible, thereby increasing switching speed. Conventional gate oxide layers may be inadequate in several respects as dimensions are continuously scaled.
Extremely thin silicon dioxide gate dielectrics exhibit undesirable phenomena such as quantum-mechanical tunneling. In the classical sense, the oxide represents a relatively impenetrable barrier to injection of electrons into the conduction-band of the silicon if they possess kinetic energies smaller than 3.1 eV. However, the electron exhibits a finite probability of crossing the barrier even if the electron does not possess sufficient kinetic energy. This probability increases with larger gate electric fields and/or thinner gate oxides. For oxide thicknesses smaller than 3 nm the direct tunneling current becomes large enough that it removes carriers faster than they can be supplied by thermal generation. As a result, silicon dioxide gate dielectrics are likely to reach a lower scaling limit of about 1.5 nm to 2 nm.
Another problem with thin gate oxides is their susceptibility to dopant diffusion from the overlying gate electrode. A polysilicon gate electrode layer is typically doped with boron for its enhanced conductivity. As the gate oxide thickness is scaled down, boron can easily penetrate through the gate oxide, resulting in instabilities in device properties. Boron penetration into gate dielectrics has such undesirable consequences as positive shifts in threshold voltage, increases in sub-threshold swing, increases in charge trapping, decreases in low-field hole mobility, and degradation of current drive due to polysilicon depletion in p-MOSFETs.
Efforts to address deficiencies of silicon dioxide include nitrogen incorporation into the gate dielectric. Silicon nitride (Si
3
N
4
) has a higher dielectric constant than SiO
2
, theoretically enabling thinner equivalent oxide thickness for gate dielectrics that are not tunnel-limited, and furthermore serves as an effective barrier against impurity diffusion. However, the interfaces between silicon nitride films and the underlying semiconductor substrate are generally of poor quality, resulting in a high density of charge trapping sites and pinholes, and attendant current leakage. As a consequence, attempts have been made to create SiO
2
and Si
3
N
4
hybrids, such as silicon oxynitride films, for use as gate dielectrics. Conventional methods of incorporating nitrogen into silicon oxide gate dielectrics are difficult to control, however, particularly for ultra-thin gate dielectrics of future generation devices
Other solutions to scaling problems include the use of high permittivity materials (high K), such as tantalum pentoxide, strontium bismuth tantalate (SBT), barium strontium tantalate (BST), etc. While exhibiting greatly increased dielectric strength, these materials have been difficult to integrate with existing fabrication technology.
Another issue raised by the continual scaling of integrated circuit dimensions is the difficulty of producing adequately conductive metal lines for wiring the circuitry within integrated circuits. One manner of simplifying the process of metallization is by employing damascene techniques. Rather than depositing blanket metal layers and etching away excess metal to leave wiring patterns, damascene processing involves forming templates for wiring by way of trenches in an insulating layer. Metal overfills the trenches and a polishing step removes excess metal outside the trenches. Metal is thus left in a desired wiring pattern within the trenches. Where contact holes or vias extending from the floor of the trenches to lower conductive elements are simultaneously filled with metal, the method is known as dual damascene processing.
Unfortunately, scaling introduces difficulties with damascene processes, particularly when fast diffusing metals like copper are employed for the metal lines and contacts. In order to prevent peeling of metal lines from the surrounding insulation and to prevent diffusion spikes causing shorts across lines, one or more lining layers are formed within the trenches (and vias, in dual damascene processing) prior to metal fill. Typically, metal adhesion layers and metal nitride barrier layers are employed. A metal seed layer may also be needed if the trenches are to be filled by electroplating.
These lining layers occupy a considerable volume of the available trenches, reducing room available for the more highly conductive metal filler. Conductivity is thus reduced relative to the same trenches filled completely with metal. Moreover, employing metal nitride liners, though advantageously containing the metal filler and preventing short circuits, has been known to induce electromigration during circuit operation, leading to voids and further reduced conductivity along the metal lines.
Accordingly, a need exists for thin films that overcome problems associated with gate dielectrics constructed of traditional materials such as silicon nitride and silicon oxide. A need also exists for improved structures and methods for containing metal within damascene trenches without excessive losses in conductivity.
SUMMARY OF THE INVENTION
The aforementioned and other needs are satisfied by several aspects of the present invention.
In accordance with one aspect of the invention, a thin film is provided in an integrated circuit. The film has a small thickness, defined between an upper surface and a lower surface. A controlled, varying composition is provided through this small thickness. Exemplary thicknesses are preferably less than about 100 Å, more preferably less than about 50 Å and can be on the order of 10 Å.
In accordance with one embodiment, the film comprises a gate dielectric for an integrated thin film transistor. In one arrangement, a silicon oxide layer is provided with a graded concentration of nitrogen. Despite the thinness of the layer, such a gradient can be maintained. Advantageously, a relatively pure silicon dioxide can be provided at the lower level for a high quality channel interface, while a high nitrogen content at the upper surface aids in resisting boron diffusion from the polysilicon gate electrode. In another arrangement, other dielectric materials can be mixed in a graded fashion to obtain desirable interface properties from one material and desirable bulk properties from another material, witho

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