Method of forming gate pattern of flash memory device...

Details Method of forming gate pattern of flash memory device... Method of forming gate pattern of flash memory device...

2007-12-21

2010-06-22

Brewster, William M. (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S717000, C438S754000

Reexamination Certificate

active

07741203

ABSTRACT:
A method of forming a gate pattern of a flash memory device may include forming a tunnel dielectric layer, a conductive layer for a floating gate, a dielectric layer, a conductive layer for a control gate, a metal electrode layer, and a hard mask film over a semiconductor substrate. The metal electrode layer may be etched such that a positive slope of an upper sidewall may be formed larger than a positive slope of a lower sidewall of the metal electrode layer. The conductive layer for the control gate, the dielectric layer, and the conductive layer for the floating gate may then be etched. High molecular weight argon gas, for example, may be used to improve an anisotropic etch characteristic of plasma. Over etch of a metal electrode layer may be decreased to reduce a bowing profile. Resistance of word lines can be decreased and electrical properties can be improved.

REFERENCES:
patent: 5437765 (1995-08-01), Loewenstein
patent: 2002/0197837 (2002-12-01), Kwak et al.
patent: 2007/0281477 (2007-12-01), Lee et al.
patent: 2008/0020583 (2008-01-01), Ueda et al.
patent: 102006012097 (2006-11-01), None

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