Method of forming gate line of semiconductor device

Details Method of forming gate line of semiconductor device Method of forming gate line of semiconductor device

2011-08-23

2011-08-23

Nguyen, Ha Tran T (Department: 2829)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S257000, C257SE21209, C257SE21158

Reexamination Certificate

active

08003508

ABSTRACT:
A method of forming a gate line of a semiconductor device, wherein when an etch process for forming a gate line is performed, a loading effect is improved, thereby enhancing the operating speed of a semiconductor device. According to a method of forming a gate line of a semiconductor device in accordance with an aspect of the invention, a stack layer is formed over a semiconductor substrate that includes a first area and a second area. Hard mask patterns are formed over the stack layer so that the hard mask patterns are denser in the first area than in the second area. Next, a loading compensation layer is formed before the stack layer is etched, or the loading compensation layer is deposited after the stack layer is partially etched. Accordingly, a loading effect occurring when the stack layer is etched can be offset.

REFERENCES:
patent: 2003/0189232 (2003-10-01), Law et al.
patent: 2008/0081412 (2008-04-01), Jung
patent: 10-2003-0053201 (2003-06-01), None
patent: 10-2003-0059418 (2003-07-01), None
patent: 10-2006-0094707 (2006-08-01), None
patent: 10-2008-0046435 (2008-05-01), None

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