Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2000-06-02
2002-06-11
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S151000, C438S159000, C438S160000
Reexamination Certificate
active
06403407
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to thin-film field-effect transistors (TFTs), and more particularly to a method of fabricating devices which self align source/drain (S/D) contacts with a gate electrode where a channel insulator is also self-aligned (i.e., a fully self-aligned TFT), and utilizes simple process modifications to minimize the time and cost of producing such a self-aligned device.
2. Description of the Related Art
In a conventional staggered inverted bottom-gate thin-film transistor (TFT), such as those used in active matrix displays, the source and drain electrodes of all TFTs are aligned globally using corner alignment marks on a surface. Such a system has a limited accuracy, so there is a misalignment offset between the underlying gate electrode and the source and drain contacts (S/D contacts or electrodes). Because the S/D contacts are not self-aligned, the degree of overlap is usually increased at the mask level to allow for these offsets. This is undesirable because it increases the source-drain to gate (S/D-G) capacitance of the devices, which in turn increases the pixel feedthrough voltage (&Dgr;Vp) in the active matrix display.
The feedthrough voltage is caused by charge stored in the TFT source to gate (S-G) capacitance (Cgs) when the pixel TFT has charged the pixel and returns to its OFF state. The &Dgr;Vp offset must be compensated for using a combination of passive elements (storage capacitors) included in the active matrix design and suitable electronic drive schemes. Any shift in S/D alignment across the active matrix may lead to incomplete compensation of &Dgr;Vp, and hence to visual artifacts in the finished display.
Because the source/drain contacts are not self-aligned, the amount of overlap on the channel insulator is increased in the mask design to insure adequate overlap even with a worst case alignment error. This is undesirable not only because it increases the feed through voltage but also because it places a lower limit on the channel length of the device. It is highly desirable to produce TFTs with shorter channel lengths due to the higher driving current which reduces the needed charging time for high resolution and high image content displays.
One method to self-align the source and drain contacts of a TFT to the gate electrode, which has been previously described in U.S. Pat. Nos. 5,156,986 and 5,340,758 as well as, a commonly assigned disclosure, entitled, “METHOD FOR FABRICATING SELF-ALIGNED THIN-FILM TRANSISTORS TO DEFINE A DRAIN AND SOURCE IN A SINGLE PHOTOLITHOGRAPHIC STEP”, U.S. Ser. No. 09/410,280, filed on Sep. 30, 1999, and incorporated herein by reference, is to use a combination of the topography of the gate metal and/or top channel insulator with a planarizing or semi-planarizing layer over the source-drain metallization. By uniformly removing a portion of the planarization layer, a portion of the metallization is exposed that is in substantial alignment with the gate metal topography, and this exposed portion may then be etched to form self-aligned source and drain electrodes.
The process window of such methods is not as wide as one would desire to be considered conservative since, in general, the photoresist applied is not perfectly planar, the process used to thin the resist is not perfectly uniform, and the thickness of the resist over the channel topography depends somewhat on the aspect ratio of the features defined.
Another method for isolating the source and drain features which relies on the thinning of a photoresist in the channel region of a TFT has been described in “A TFT manufactured by 4 masks process with new photolithography” by C. W. Han et al., Asia Display '98 pp. 1109-1112 (1998). In this work, thinning of the resist in the channel was achieved by exposure through a gray scale mask, which limited the dose in the channel region such that only a portion of the resist there was removed at development, in contrast to regions which received either no exposure or the full dose, where, in the case of positive resist, these regions had a thickness greater than that of the channel region or no thickness remaining, respectively. In this case, however, the gray scale exposure is used to: a) fabricate the active a-Si island of a back-channel etch (BCE) type TFT and, through removal of only the thin channel photoresist in a subsequent step, to b) define the back-channel cut defining the source and drain contacts. In this way, the active island and channel cut are achieved in a single photolithographic step which simplifies the process. The TFT so produced, however, does not specifically make use of the topography of the gate electrode, and since the TFT is of the BCE type, there is no top channel insulator available to add extra topography. Thus the TFT described is not self-aligned and so does not enjoy the advantages of self-alignment described above.
Therefore, a need exists to produce fully self-aligned TFTs, e.g., with self-aligned S/D contacts and a channel insulator self-aligned to a gate electrode to reduce or eliminate the problems outlined above. In addition to reducing S/D-G capacitance and increasing pixel charging uniformity, it is also desirable to produce a TFT with a shorter channel since a shorter channel results in more current drive available for pixel charging and hence a shorter charging time which is important for high-resolution, high-performance active matrix displays.
SUMMARY OF THE INVENTION
In accordance with the present invention, methods are provided for improving thin film transistor fabrication processes. One improvement includes forming a fully self-aligned TFT using back exposure of a gate electrode to self-align the channel region to the gate electrode and then using the topography of the channel insulator, a photoresist layer which is partially planarized over the source and drain metallization, a modification of the usual photomask which is used to define the photoresist for etching the source and drain metallization, to include a gray level region overlapping the topography of the channel insulator, and a uniform resist etching step prior to etching the source and drain metallization. The density of the gray level mask region and the amount of resist etched are chosen so that the thickness of the resist which is exposed sufficiently to be removed by the developer along with that etched exceeds the thickness of the resist on the channel insulator and gate metal topography but is less then the thickness of the resist on areas without the channel insulator topography. Since the channel insulator is formed with a tapered edge, there is a transition region between these two thickness'of resist and the overlap distance of the source and drain contacts over the gate electrode is determined by the combination of the actual thickness of the resist removed and the distance between the edge of the channel insulator and the gate metal. Both of these distances can be adjusted by changing the processing conditions. The addition of the uniform etching step allows the process window defined by exposure and density of the mask gray scale regions to be effectively widened, since it removes the penalty of underexposure in the channel region. The process may then be chosen to be more conservative, since any resist left in the channel region after development will be considerably thinner than resist left elsewhere due to the combination of topography and gray scale exposure, and thus removable by uniform resist etching would take place in less time than would be case using topography alone.
A method for opening resist in raised areas of a semiconductor device, in accordance with the present invention, includes forming a conductive layer over a channel insulator layer to form a raised portion which includes a height above a substantially planar surrounding area, the channel insulator layer being aligned to a gate electrode, forming a photoresist layer over the raised portion and the surrounding area, and patterning the photoresist by emplo
Andry Paul Stephen
Colgan Evan George
Kinoshita Hisanori
Kitahara Hiroaki
Libsch Frank R.
F. Chau&Associates, LLP
Little Craig P.
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