Method of forming floating gate of memory device

Details Method of forming floating gate of memory device Method of forming floating gate of memory device

2004-02-26

2004-11-02

Booth, Richard A. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S594000, C438S259000, C438S963000, C438S704000

Reexamination Certificate

active

06812120

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The present invention generally relates to a method of forming a memory device. More particularly, the present invention relates to a method of forming a floating gate of a memory device.
2. Description of the Related Art
In recent years, flash memory device has become the main stream of the non-volatile memory device because flash memory device allows multiple data writing, loading and erasing operations. In addition, stored data can be preserved even when the power supply of the memory device is removed.
In a conventional flash memory device, generally the floating gate and the control gate of a stacked gate structure are manufactured with doped polysilicon. Moreover, the floating gate and the control gate are separated by an inter-gate dielectric layer. In addition, the floating gate and the substrate are separated by a tunnel oxide layer.
For writing data in a flash memory, a bias voltage is applied to the control gate and the source/drain regions so that electrons are injected into the floating gate. For reading data stored in the flash memory, an operating voltage is applied to the control gate, and the charging condition of the floating gate will effect the on/off state of the channel corresponding to the binary data “0” or “1”. For erasing data stored in the flash memory, the voltage of the substrate, drain (source) or the control gate is raised so that electrons in the floating gate will move into the substrate or drain (source) via the tunnel oxide layer due to the tunneling effect. The erasing method is generally known as “substrate erase” or “drain (source) side erase”. Alternatively, electrons in the floating gate can also move into the control gate via the inter-gate dielectric layer.
However, when a data erasure operation of a flash memory is performed, since the amount of the electrons drained from the floating gate is not easy to control, if the electrons are overly drained, the floating gate will be positively charged, and this condition is so-called the over erase. When the floating gate is extremely overly erased, the channel under the floating gate will be in continuously conducting state even when the operating voltage is not applied, and thus the error in the data may occur. Therefore, in order to resolve the over erase problem, a split gate is provided to the flash memory, i.e., a select gate (or erase gate) is disposed on the sidewall of the control gate and floating gate. Moreover, another inter-gate dielectric layer is disposed between the select gate and the control gate, and between the floating gate and the substrate. Therefore, when the over erase problem occurs and that the channel under the floating gate is conducted even when the operating voltage is not applied to the control gate, the channel under the select gate is in off-state. Therefore, the drain and source are not conducted and the error in the data can be effectively prevented.
However, if the shape of the corner of both sides of the floating gate is not sharp enough, when a data erasing operation of the flash memory is performed, the electric field on the corner of both sides of the floating gate is not high enough, and therefore a longer time is required for erasing the data. Conventionally, several methods for improving the shape of the corner of the floating gate are provided, for example, one such method is being disclosed in the U.S. Pat. No. 6,429,075. Referring to FIG.
1
and
FIG. 2
, a conventional memory device including a first isolation layer
20
, a substrate
12
, a floating gate
22
and a second isolation layer
26
is provided. The first isolation layer
20
is disposed over the substrate
12
, the floating gate
22
is disposed over the first isolation layer
20
, and the second isolation layer
26
is disposed over the floating gate
22
. Next, a thermal oxidation process is performed under a temperature of about 800° C. to 900° C. to form a silicon oxide layer
27
, and as shown in
FIG. 2
, a sharp corner
29
is formed on a corner of both side of the floating gate
22
. However, since the temperature of the thermal oxidation process is performed at a high temperature, and therefore the thermal budget of the thermal process is high. Accordingly, the method described above is not ideal. Furthermore, in the process of forming trench of memory cells, the thermal oxidation process for growing the silicon oxide layer cannot be easily controlled.
SUMMARY OF INVENTION
Accordingly, one object of the present invention is to provide a method of forming a floating gate of a memory device having a capability of promoting the erasing speed.
In accordance with the above objects and other advantages of the present invention, a method of forming a floating gate of a memory device is provided. A substrate having at least an active region, a device isolation structure, a pad layer formed over the active region, a mask layer formed over the pad layer, and a trench formed in the mask layer, the pad layer and the substrate. A tunnel oxide layer is formed on a surface of the trench, and a conductive layer is filled within the trench. Next, an isotropic etching process is performed to remove a portion of the conductive layer such that a shape of a top surface of a remaining conductive layer within the trench has a concave shape profile. Next, an anisotropic etching process is performed to remove a portion of the conductive layer within the trench. According to an embodiment of the present invention, during the anisotropic etching process, polymer residues are generated as byproduct, which gets deposited on a sidewall of the trench and serves as an etching mask. The anisotropic etching is continued until a portion of the tunnel layer is exposed. Next, the byproduct polymer residues are removed to form a first floating gate and a second floating gate on a sidewall of the trench, wherein a top corner of the first floating gate and the second floating gate has a sharp edge.
According to an embodiment of the present invention, the floating gate having a top corner with a sharp edge is formed in a two-etching step process. According, a thermal oxidation process for forming the sharp top corner of the floating gate as in the case of the conventional process can be effectively avoided. Further, the deposition of the polymer residues generated during the second etching process deposited on the sidewall in a self-aligned manner and serves as an etching mask protecting the contour of the top corner of the floating gate.
Furthermore, the top corner of the first floating gate or the second floating gate of the present invention has a sharp edge. Thus, when the flash memory cell of the present invention performs the erasing of data, the sharp edge can generate a higher electric field so that the electrons can be drained out from the sharp edge. Therefore, the time required for erasing data can be substantially reduced, and also the voltage required for the erasing can be substantially reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 6093606 (2000-07-01), Lin et al.
patent: 6281103 (2001-08-01), Doan
patent: 6429075 (2002-08-01), Yeh et al.
patent: 6639269 (2003-10-01), Hofmann et al.
patent: 6720219 (2004-04-01), Huang
patent: 2003/0219943 (2003-11-01), Lin et al.
patent: 2004/0097036 (2004-05-01), Hsiao et al.

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