Method of forming fine patterns in semiconductor device and...

Details Method of forming fine patterns in semiconductor device and... Method of forming fine patterns in semiconductor device and...

2005-12-30

2009-10-13

Ghyka, Alexander G (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S585000, C257SE21598

Reexamination Certificate

active

07601622

ABSTRACT:
There are provided a method of forming fine patterns in a semiconductor device, and a method of forming a gate with a fine critical dimension using the same. In the method of forming fine patterns in a semiconductor device, a plurality of sidewall buffer patterns are formed on a gate insulating layer formed on a substrate, wherein the plurality of the sidewall buffer patterns are spaced apart from each other by a predetermined distance. A sidewall layer is deposited on the sidewall buffer patterns as well as the gate insulating layer. The sidewall layer is etched such that sidewall patterns remain on sidewalls of the sidewall buffer patterns.

REFERENCES:
patent: 4776922 (1988-10-01), Bhattacharyya et al.
patent: 4784718 (1988-11-01), Mitani et al.
patent: 5786256 (1998-07-01), Gardner et al.
patent: 6255202 (2001-07-01), Lyons et al.
patent: 6383952 (2002-05-01), Subramanian et al.
patent: 6664154 (2003-12-01), Bell et al.
patent: 2004/0198031 (2004-10-01), Lin et al.

Affiliated with

Also associated with

Rating

Method of forming fine patterns in semiconductor device and... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming fine patterns in semiconductor device and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming fine patterns in semiconductor device and... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4117278