Method of forming fine metal pattern and method of forming...

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S622000, C438S631000, C438S639000, C438S698000, C438S759000, C257SE21244, C257SE21444, C257SE21576, C257SE21579, C257SE21637, C257SE23144, C257SE23154, C257SE29158, C257SE29162, C257SE29165

Reexamination Certificate

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07575995

ABSTRACT:
There are provided a method of forming a fine metal pattern and a method of forming a metal line using the same. In the method of forming a fine metal pattern, a substrate is prepared where a first interlayer insulating layer is formed. A via plug is formed on the first interlayer insulating layer. A plurality of sidewall buffer patterns are formed on the first interlayer insulating layer having the via plug, wherein the plurality of the sidewall buffer patterns are spaced apart from each other by a predetermined distance. The sidewall layer is deposited on the first interlayer insulating layer and the sidewall buffer patterns. The sidewall layer is etched such that sidewall patterns remains on sidewalls of the sidewall buffer patterns.

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patent: 5183800 (1993-02-01), Nakagawa
patent: 5643837 (1997-07-01), Hayashi
patent: 6635528 (2003-10-01), Gilbert et al.
patent: 7132364 (2006-11-01), Kim
patent: 7160767 (2007-01-01), Brask et al.
patent: 7473632 (2009-01-01), Ueda
patent: 2003/0017692 (2003-01-01), Noguchi et al.
patent: 100140485 (1998-03-01), None
Office Action from the Korean Intellectual Property Office, dated May 12, 2006, in related Korean Patent Application No. 10-2004-0114637.

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