Method of forming field effect transistor and structure...

Details Method of forming field effect transistor and structure... Method of forming field effect transistor and structure...

2006-04-11

2006-04-11

Kang, Donghee (Department: 2811)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S157000, C438S159000, C438S163000, C438S201000, C438S223000, C438S241000, C257S327000, C257S329000, C257S331000, C257S348000

Reexamination Certificate

active

07026196

ABSTRACT:
A method for forming a field effect transistor includes: forming a conductive region on an isolation layer formed on a substrate, and a cap dielectric layer on the conductive region; forming a sacrificial dielectric layer over the isolation layer and the cap dielectric layer, and on sidewalls of the conductive region; removing a portion of the sacrificial dielectric layer on the cap dielectric layer; removing the cap dielectric layer; removing remaining portions of the sacrificial dielectric layer; forming a gate on the conductive region; and forming source/drain (S/D) regions within the conductive region and adjacent to the gate. A field effect transistor includes a conductive region over an isolation layer formed on a substrate, the conductive region being substantially without undercut at the region within the isolation layer beneath the conductive region; a gate on the conductive region; and S/D regions within the conductive region and adjacent to the gate.

REFERENCES:
patent: 6413802 (2002-07-01), Hu et al.
patent: 6489201 (2002-12-01), Yoon
patent: 6562665 (2003-05-01), Yu
Fu-Liang Yang et al., “25 nm CMOS Omega FETs”, 2002 IEEE, 4 pages.
S. Monfray et al., “50 nm—Gate All Around (GAA)—Silicon On Nothing (SON)—Devices: A Simple Way to Co-integration of GAA Transistors within bulk MOSFET process”, 2002 IEEE, 2002 Symposium on VSLI Technology Digest of Technical Papers, 2 pages.
J.P. Colinge et al., “SOI Devices for Sub-0.1 um Gate Lengths”, 2002 IEEE, 2002 Proc. 23rd International Conference on Microelectronics (Miel 2002), vol. 1, 2 pages.
Fu-Liang Yang et al., “35 nm CMOS FinFets”, 2002 IEEE, 2002 Symposium on VLSI Technology Digest of Technical Papers, 2 pages.

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