Method of forming ferroelectric random access memory device

Details Method of forming ferroelectric random access memory device Method of forming ferroelectric random access memory device

2002-07-17

2004-07-20

Nguyen, Thanh T. (Department: 2813)

Semiconductor device manufacturing: process

Having magnetic or ferroelectric component

C438S238000, C438S239000, C438S240000, C438S381000

Reexamination Certificate

active

06764862

ABSTRACT:

RELATED APPLICATION
This application relies for priority upon Korean Patent Application No. 2001-62848, filed on Oct. 12, 2001, the contents of which are herein incorporated this by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to a method of forming a ferroelectric random access memory (FRAM) device, and more particularly to a method of forming a FRAM having a capacitor over bit-line (COB) structure.
BACKGROUND OF THE INVENTION
When an external electric field is applied to a ferroelectric substance, a polarization is generated in the ferroelectric substance. When the external electric field is removed, the polarization largely remains. The direction of a self polarization generated therein can be controlled by changing the external electric field. The ferroelectric substance may be formed by processing a high dielectric material such as PZT (Pb(Zi,Ti)O
3
) and SBT (SrBi
2
Ta
2
O
9
). These properties of the ferroelectric substance are similar to a basic principle of binary memories widely used. In order to form a ferroelectric substance, a high-dielectric material such as PZT or SBT needs to exhibit a ferroelectric structure called a “perovskite structure”. In a conventional method of forming such a perovskite structure, a high-dielectric material is stacked in an amorphous state, heated to about 700° C. under an oxidation ambient, and crystallized.
The FRAM structure is very similar to that of a DRAM. Thus, a cell array region is divided by horizontal and vertical core regions and a peripheral region is located around the cell array region. In the core region, interconnections formed over a memory cell device such as a transistor and a capacitor are connected with a semiconductor substrate, a gate line or a bit line. In general, the interconnection is located over the capacitor and the bit line, and the gate line and the semiconductor substrate are located below the capacitor. Thus, the interconnections among conductive lines and conductive regions are made through contacts.
Aluminum is frequently used for such contacts in a semiconductor device. The aluminum is typically stacked at the semiconductor substrate by a sputtering technique that forms the interconnection and the contact plug simultaneously. But, the aluminum has a poor gap-fill characteristic and may leave voids when a high-aspect ratio contact hole is filled. In order to solve this problem, an Al-flow technique may be used. But this makes the process more complicated and results in deterioration of the semiconductor device during the heat flow step.
Thus, the contact plug and the interconnection are preferably formed by sputtering at room temperature. But, to avoid voids, the aspect ratio or depth of the contact hole should be decreased. In order to decrease the depth of the upper interconnection contact, a pad or a stud is formed at a conductive region of the core in the bit line contact or the capacitor contact. In this case, the depth of the contact hole can be decreased by the height of the pad or stud. The pad formed at the conductive region of the core is composed of polysilicon or tungsten, the same material used to form the contact pad, the bit line pad, and the capacitor contact at the cell array region.
However, after forming the capacitor contact at the cell array region, a capacitor lower electrode layer, a ferroelectric layer and a capacitor upper electrode layer are formed and patterned. Then, to form a perovskite structure of a ferroelectric layer or for an annealing process, thermal treatment is required under an oxidation ambient. But, since the capacitor is not formed at the core region, the pad or the stud is exposed during the thermal treatment process under the oxidation ambient.
FIGS. 1 and 2
are cross-sectional views illustrating two examples in which the top of a stud is oxidized during formation of a capacitor in a conventional ferroelectric memory device.
Referring to
FIG. 1
, a cell transistor having a gate
13
and source/drain regions is formed at a cell memory region of a semiconductor substrate over an isolation layer
11
. A contact pad
14
is formed between the gates
13
. A first insulation layer
15
is formed and patterned to form a contact hole exposing a bit line contact pad. Simultaneously, even at a core region, another contact hole is formed to expose a conductive region. A tungsten layer is stacked and patterned to form a bit line and a bit line contact (not shown in FIG.
1
). The contact hole formed at the core region is filled with a lower stud
17
of tungsten. A second insulation layer
19
is stacked over the bit line and patterned to form a capacitor contact hole exposing a capacitor contact pad and to form a contact hole exposing the lower stud
17
at the core region. Tungsten is stacked on the resultant structure by a CVD technique and polished by a CMP technique, thereby forming a capacitor contact plug
21
at the cell memory region and simultaneously forming an upper stud
23
at the core region.
A conductive adhesive layer (not shown in FIG.
1
), a lower electrode layer, a ferroelectric layer, and an upper electrode layer are sequentially stacked over the capacitor contact plug
21
. These layers are patterned to form a ferroelectric capacitor
37
comprising a lower electrode
31
, a ferroelectric pattern
33
, and an upper electrode
35
as shown in FIG.
1
. In the core region, these layers are all removed during the patterning process, thereby exposing the surface of the upper stud
23
. The ferroelectric layer typically is damaged during the patterning process but cured during an annealing process under an oxidation ambient. The upper stud
23
of the core region is thermally treated by exposure to the oxidation ambient, so that the surface of the upper stud
23
is oxidized.
Referring to
FIG. 2
, the capacitor contact plug
21
of the cell array region and the upper stud
23
of the core region are formed by the same process as described above in connection with FIG.
1
.
The conductive adhesive layer (not shown in
FIG. 2
) and a lower electrode layer may be sequentially stacked on the capacitor contact plug
21
and patterned. A barrier layer
32
and a material layer
34
are stacked on a lower electrode
31
and polished by a CMP technique to expose the surface of the lower electrode
31
. Then, a gap between the lower electrodes
31
is filled with the barrier layer
32
and the material layer
34
. A ferroelectric layer
33
is stacked over substantially the entire surface of the semiconductor substrate. The conductive adhesive layer, the lower electrode layer and the material layer, which have been stacked over the upper stud
23
, are removed during each patterning process, thereby leaving only the ferroelectric layer
33
on the upper stud
23
.
Ferroelectric layer
33
is formed by a sol-gel transformation or stacked by a CVD technique or a sputtering technique. When the ferroelectric layer
33
is stacked by the CVD technique, the condition of the stacking process should include a high temperature and an oxidation ambient. When other techniques are used for forming the ferroelectric layer
33
, after being stacked, the ferroelectric layer
33
is treated under an oxidation ambient of high temperature. The ferroelectric layer
33
acts as not an oxygen barrier layer but an oxygen carrier layer, thereby oxidizing the surface of the upper stud
23
in contact with the ferroelectric layer
33
.
Since the upper stud
23
exposed to the oxidation ambient of high temperature is composed of polysilicon or tungsten, if the surface thereof is oxidized, an insulation layer is formed thereat, and a popping phenomenon occurs due to volume expansion. Also, if another layer is present on the upper stud
23
, a lifting phenomenon may occur (also due to volume expansion), so that the layer may be lifted. These phenomena interfere with a normal electrical connection between the interconnection contact and the semiconductor substrate.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a meth

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