Fishing – trapping – and vermin destroying
Patent
1986-04-09
1988-03-08
Roy, Upendra
Fishing, trapping, and vermin destroying
357 34, 357 67, 437 33, 437162, 437200, 437928, 437931, H01L 2712, H01L 21265
Patent
active
047299657
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
This invention relates generally to a method of producing a semiconductor device, and more particularly to a method of easily producing a semiconductor device which is suitable for producing a bipolar semiconductor device having a high packing density.
BACKGROUND ART
Many methods of producing bipolar type semiconductor devices have been proposed to this date in order to improve the operating speed and packing density of the devices, as is well known in the art.
For instance, a method has been proposed which forms a base contact and an emitter by self-alignment so as to improve the packing density (T. Sakai et al, JJAP, vol. 20-1, 155, 1981).
Since the base contact and the emitter can be formed by self-alignment as described above, this method has a characterizing feature in that a bipolar transistor having an extremely small occupying area but having high performance can be obtained without using fine lithography.
However, this method is not without drawbacks, in that the production process is complicated, and bipolar transistors having uniform characteristics cannot be formed easily because the emitter area is likely to vary. Therefore, a method which can be practised more simply and more easily has been desired.
DISCLOSURE OF INVENTION
It is an object of the present invention to provide a method of producing a semiconductor device which eliminates the problems with the prior art methods described above and can produce bipolar semiconductor devices having a high packing density with a high yield.
To accomplish the object described above, the present invention first forms a hole for a base contact at a peripheral portion of a region in which an emitter is to be formed, then forms an emitter hole by lithography at a position spaced apart from the base contact hole by a predetermined distance necessary for securing a high breakdown voltage, and extends an external base consisting of a polycrystalline silicon film or a metal silicide film from the base contact hole to a position below the wiring.
The lithography technique is practised in the following manner, as is well known in the art.
A film whose solubility changes when it is irradiated with light, an electron beam or X-rays (i.e., resist film) is coated on the entire surface of a meaterial to be worked such as a semiconductor substrate, an insulating film, a metal film or a polycrystalline silicon film, and the light, electron beam or X-rays are then radiated selectively to desired portions of the resist film so as to change the solubility of the irradiated portions. If the resist is of a negative type, the solubility of the irradiated portions drops, and if it is of a positive type, the solubility increases.
The portions of the resist film having a high solubility are removed by development, and the exposed portions of the material to be worked are etched.
In this manner, the desired portions of the material to be worked can be selectively etched and a desired pattern can be formed.
The method which radiates light to change the solubility of the resist film is referred to as "photolithography". Similarly, the methods which radiate the electron beam and X-rays are referred to as "electron beam lithography" and "X-ray lithography", respectively.
BRIEF DESCRIPTION OF DRAWINGS
FIG. 1 is a process diagram showing one embodiment of the present invention;
FIGS. 2, 3 and 4 are sectional view, plan view and diagram useful for explaining the positional deviation of an emitter in the present invention, respectively;
FIG. 5 is a process diagram showing another embodiment of the present invention; and
FIG. 6 is a sectional view showing still another embodiment of the present invention.
BEST MODE FOR CARRYING OUT THE INVENTION
EXAMPLE 1
FIGS. 1(a) through 1(f) are process diagrams useful for explaining one embodiment of the present invention.
First of all, a collector buried layer 2 having a conductivity type opposite to that of a silicon substrate 1 is formed by knowm methods on the surface of the silicon substrate 1 as shown in FIG.
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Hasegawa Norio
Nishizawa Hirotaka
Okazaki Shinji
Sagara Kazuhiko
Takakura Toshihiko
Hitachi , Ltd.
Roy Upendra
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