Method of forming element isolation region

Details Method of forming element isolation region Method of forming element isolation region

1995-07-07

1997-05-20

Dang, Trung

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Recessed oxide by localized oxidation

438440, H01L 2176

Patent

active

056311893

ABSTRACT:
According to this method, before a silicon nitride (Si.sub.3 N.sub.4) layer having a thickness of about 200 nm and serving as a field oxidation (selective oxidation) mask is formed, nitrogen-doped amorphous silicon is deposited to form a silicon layer having a thickness of about 50 nm and serving as an underlying layer of the silicon nitride layer.

REFERENCES:
patent: 4016007 (1977-04-01), Wada et al.
patent: 4541167 (1985-09-01), Havemann
patent: 5192707 (1993-03-01), Hodges et al.
patent: 5338750 (1994-08-01), Tuan et al.
patent: 5397732 (1995-03-01), Chen
"Isolation Process Using Polysilicon Buffer Layer for Scalled MOS/VLSI" Yu-Pin Han et al, Extended Abstracts vol. 84-1, Spring Meeting, Cincinnati, Ohio, May 6-11, 1984.

Affiliated with

Also associated with

Rating

Method of forming element isolation region does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming element isolation region, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming element isolation region will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1723597