Method of forming dynamic random access memory circuitry and dyn

Details Method of forming dynamic random access memory circuitry and dyn Method of forming dynamic random access memory circuitry and dyn

1998-07-20

1999-11-02

Dutton, Brian

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257301, 257303, 257532, 257534, H01L 2968, H01L 27108

Patent

active

059775785

ABSTRACT:
A semiconductor processing method of forming dynamic random access memory circuitry includes, a) providing an electrically conductive capacitor cell plate substrate; b) providing an electrical insulative layer over the cell plate; c) providing a layer of semiconductive material on the insulative layer thereby defining a semiconductor-on-insulator (SOI) layer; d) patterning and etching the SOI layer to define active area region islands and isolation trenches between the islands; e) filling the isolation trenches with insulative material; f) providing capacitor openings through the SOI layer and insulative layer into the cell plate substrate; g) providing a capacitor dielectric layer over the cell plate substrate within the capacitor openings; h) providing respective capacitor storage nodes over the dielectric layer within the capacitor openings, the respective storage nodes being in ohmic connection with the SOI layer; i) after providing the storage nodes, filling any remaining portions of the capacitor container openings with insulative material; j) providing a gate dielectric layer atop the SOI layer islands; k) providing conductive word lines over the gate dielectric layer on the islands and over the filled isolation trenches; l) providing opposing FET source and drain regions within the SOI layer; and m) providing bit lines outwardly of the word lines, the bit lines connecting with selected drain regions. Also contemplated is a DRAM array having sources and drains formed within an SOI layer, wherein capacitors of the array comprise trenches formed within a monocrystalline substrate, with the substrate comprising a common cell plate of the capacitors.

REFERENCES:
patent: 4688064 (1987-08-01), Ogura et al.
patent: 4829017 (1989-05-01), Malhi
patent: 4855952 (1989-08-01), Kiyosumi
patent: 4873560 (1989-10-01), Sunami et al.
patent: 5097381 (1992-03-01), Vo
patent: 5442211 (1995-08-01), Kita
patent: 5442584 (1995-08-01), Jeong et al.
patent: 5466625 (1995-11-01), Hsieh et al.
patent: 5470778 (1995-11-01), Nagata et al.
patent: 5504027 (1996-04-01), Jeong et al.
patent: 5508219 (1996-04-01), Bronner et al.
patent: 5508541 (1996-04-01), Hieda et al.
patent: 5525531 (1996-06-01), Bronner et al.
patent: 5555520 (1996-09-01), Sudo et al.
patent: 5606188 (1997-02-01), Bronner et al.
patent: 5650957 (1997-07-01), Choi
patent: 5661320 (1997-08-01), Moriya
patent: 5770875 (1998-06-01), Assaderaghi et al.
Nishihara, Toshiyuki et al., "A Buried Capacitor Cell With Bonded SOI For 256-Mbit and 1-Gbit DRAMs", Solid State Technology, Jun. 1994, pp. 89-94.

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