Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-07-08
2004-01-06
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S672000, C438S674000
Reexamination Certificate
active
06673712
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of Invention
The present invention relates to a method of forming a semiconductor device and a structure formed by the same. More particularly, the present invention relates to a method of forming a dual-implanted gate and a structure formed by the same.
2. Description of Related Art
At present, the gate of most semiconductor devices has a stack structure that includes a doped polysilicon layer and a metallic layer or a metal silicide layer. To manufacture a semiconductor device having both n-doped and p-doped polysilicon gates, the so-called “dual-implanted gate”, polysilicon material is first deposited over a substrate. An ion implantation is carried out to implant ions into the substrate such that n-type dopants are implanted into NMOS region and p-type dopants are implanted into PMOS region. Thereafter, a layer of tungsten or tungsten silicide (WSi
x
) is formed over the doped polysilicon layer. Finally, an etching operation is conducted to pattern out a dual-implanted gate structure.
However, the deposition of tungsten or tungsten silicide over the polysilicon layer often leads to an out-diffusion of dopant ions. This is because the grain boundary of the tungsten or tungsten silicide layer is relatively large. Hence, the n-type or p-type ions within the doped polysilicon layer can easily diffuse through the tungsten or tungsten silicide layer into another polysilicon layer. Under such circumstances, the concentration of dopants within the polysilicon layer is likely to drop, leading to a degradation of device performance.
In addition, if a tungsten layer is formed over the polysilicon layer, difference in material properties between tungsten and polysilicon may lead to the production of gates having an irregular shape after patterning through an etching operation. Similarly, due to a difference in material properties between tungsten and polysilicon, the tungsten layer may peel off from the doped polysilicon layer after a subsequent thermal processing operation.
SUMMARY OF INVENTION
Accordingly, one object of the present invention is to provide a method of forming a dual-implanted gate capable of preventing doped ions having different electrical states from cross diffusing through an overhead metallic layer.
A second object of this invention is to provide a method of forming a dual-implanted gate capable of preventing any change in concentration of doped ions inside a doped polysilicon layer.
A third object of this invention is to provide a method of forming a dual-implanted gate and a structure formed by the same, which is capable of preventing the degradation of device performance.
A fourth object of this invention is to provide a method of forming a dual-implanted gate and a structure formed by the same, which is capable of preventing the formation of gates having an irregular shape.
A fifth object of this invention is to provide a method of forming a dual-implanted gate and a structure formed by the same, which is capable of preventing an overhead metallic layer from peeling off a doped polysilicon layer.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of forming a dual-implanted gate. The method includes the following steps. First, a substrate having a gate oxide layer thereon is provided. A polysilicon layer, a sacrificial layer and a mask layer are sequentially formed over the substrate. The polysilicon layer, the sacrificial layer and the mask layer are patterned to form a first structure for forming an N-type gate and a second structure for forming a P-type gate. A dielectric layer is formed over the substrate covering the first and the second structure. The dielectric layer is planarized to expose the upper surface of the mask layer in the first and the second structure. The mask layer is removed to form a plurality of trenches. The first and the second structure are implanted using ions having different electrical states. The sacrificial layer is removed. Thereafter, a barrier layer is formed over the substrate. A metallic layer is formed over the substrate completely filling the trenches. The metallic layer is planarized to remove excess metal outside the trench. The exposed barrier layer is removed and then the dielectric layer is removed to form a plurality of gate structures. Finally, spacers may form on the sidewalls of the gate structures.
In this invention, a barrier layer is formed over the doped polysilicon layer before forming the metallic layer. Thus, dopants having different electrical states within the doped polysilicon layer are prevented from cross diffusing with the overhead metallic layer. Hence, changes in dopant concentration within the doped polysilicon layer and the peeling of the metallic layer away from the doped polysilicon layer are prevented. Ultimately, device performance can be maintained. Furthermore, by enclosing the sidewall of the metallic layer with a barrier layer, the formation of irregular-shaped gates due to a difference in material properties between the metallic layer and the polysilicon layer is largely avoided.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a dual-implanted gate. The dual-implanted gate includes a stack structure and a spacer on a substrate. The stack structure includes a polysilicon bottom layer, a barrier layer and a metallic layer, the metallic layer being surrounding by the barrier layer. The spacer is formed on the stack layer over the substrate and the stack structure is enclosing by the spacer.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a dual-implanted gate. The dual-implanted gate includes a plurality of stack structures and a spacer on a plurality of corresponding spacers. The stack structure includes a polysilicon bottom layer, a barrier layer and a metallic layer, the metallic layer being surrounding by the barrier layer. The spacer is formed on the stack layers over the substrate and each of the stack structure is enclosed by the corresponding one of the spacers.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 6156651 (2000-12-01), Havemann
patent: 6215190 (2001-04-01), Bruce et al.
patent: 6258711 (2001-07-01), Laursen
Jiang Chyun IP Office
Lindsay Jr. Walter L.
Niebling John F.
ProMos Technologies Inc.
LandOfFree
Method of forming dual-implanted gate and structure formed... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming dual-implanted gate and structure formed..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming dual-implanted gate and structure formed... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3263035