Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-11-02
2001-07-17
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S333000, C257S288000, C257S390000, C257S401000, C257S402000, C257S411000, C438S154000, C438S155000, C438S197000, C438S694000
Reexamination Certificate
active
06262455
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the manufacture of semiconductor devices and, more particularly, to the manufacture of multiple field effect transistor (FETs) devices on a single wafer having layers of dielectric of varying thickness.
BACKGROUND OF THE INVENTION
In recent years, the semiconductor industry has realized tremendous advances in technology that have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of hundreds of MIPS (millions of instructions per second) to be packaged in relatively small, air-cooled semiconductor device packages. Many of the integrated circuits formed on semiconductor substrates are comprised of several circuit functions on the single chip. Such devices include, for example, nonvolatile memory (NVM) memory devices and DRAMs (dynamic random access memory) which are composed of an array of memory cells for storing digital information. The peripheral circuits on these devices are typically composed of logic circuits for addressing the memory cells, while other peripheral circuits function as read/write buffers and sense amplifiers. Commercially, the drive for increased portability and continuous use while reducing size and weight of electronic hand-held devices has put more pressure on chip manufacturers to find ways to handle these requirements while reducing the chip size.
To improve performance and optimize these devices, it is very desirable in the electronics industry to provide FETs that have both thin and thick gate dielectric layers, usually oxide layers. A thin gate dielectric layer is used in the peripheral (logic) circuits to enhance FET device performance, while it is desirable to provide a thicker gate dielectric layer for the higher gate voltage requirements of analog and I/O circuits. For example, the FETs in the logic circuits would have a gate voltage of about 3.3 volts. On the other hand, the access transistor in analog and I/O circuits often require a significantly higher gate voltage.
A current approach to making these types of devices uses a grow-etch-grow process. In using the grow-etch-grow process to form the thick and thin gate oxides, the thick oxide layer is partially grown first. A photoresist mask is then provided over the thick gate layer region while etching the oxide from the thin gate regions; the entire wafer is then exposed to thin gate oxide growth. One drawback to this method, however, is that the photoresist mask contaminates the oxide and degrades the device's electrical characteristics. One such contaminant is the mobile sodium (Na) ion in the gate oxide that affects the long-term stability of the gate voltage on the is FET. Another drawback to this method is that it leads to higher defects in the oxide layer, as the initial thick gate oxide layer is exposed to the thin gate oxide preclean process. Attack of the thick gate oxide during the thin gate preclean process leads to formation of defects in the thick gate oxide.
There is a need to provide a method for forming the thin and thick gate oxides on a semiconductor substrate without the photoresist layer causing contamination of the gate oxide and without damaging the thick oxide layer during a thin gate preclean process.
SUMMARY OF THE INVENTION
The present invention is directed to a multiple layer gate oxide manufacturing method that does not expose the thick gate oxide to a photoresist mask and its contaminants, and does not expose the thick gate oxide to attack by etching chemicals during the thin gate preclean process. Embodiments of the invention provide the advantage of reducing the defect density in the thick gate oxide (or dielectric) layer without adding significant process complexity in manufacturing devices with thin and thick gate regions.
An example embodiment of the present invention is directed to a method of manufacturing a semiconductor structure that includes providing a first layer of a dielectric over a semiconductor material. The first layer is covered with a protective second dielectric layer that is adapted to mask the first layer. The first and second layers are then removed over a region of the semiconductor material, using the second layer to protect the first layer, therein leaving the region of semiconductor material substantially exposed. A third layer of dielectric material is formed (e.g., grown) over the first and second layers and the adjacent exposed semiconductor material region; a gate material is then deposited over the third dielectric layer. Finally, an etching step is performed that etches through the gate material and underlying layers to the semiconductor material to form a thick gate region and a thin gate region.
Another example embodiment of the present invention is directed to a method of manufacturing a semiconductor device that includes providing a first layer of a dielectric material over a semiconductor material. The first layer is covered with a protective second dielectric layer that is adapted to mask the first layer, while a third dielectric layer is grown over the second layer. A photoresist layer is formed over a portion of the third layer and then a portion of the third layer not covered by the photoresist layer is removed. The photoresist layer is then removed, thereby forming a dielectric mask from the third layer that is disposed over a portion of the second layer. Next, a portion of the second layer not covered by the dielectric mask is removed, leaving a portion of the first layer adjacent to the second and third layers substantially exposed. The dielectric mask and the exposed portion of the first layer are removed, leaving an exposed semiconductor region adjacent the first and second layers. A fourth layer of dielectric material is formed over the first and second layers and the adjacent exposed semiconductor material region; a gate material is then formed over the fourth dielectric layer. Finally, the gate material layer is etched through to the semiconductor material to form a thick gate region and a thin gate region on the semiconductor material.
The above summary of the present invention is not intended to describe each possible embodiment or every implementation of the present invention. The figures, and the detailed description that follows, more particularly exemplify these embodiments.
REFERENCES:
patent: 5668035 (1997-09-01), Fang et al.
Han et al., “Electrical Characteristics and Reliability of Sub 3nm Gate Oxides Grown on Nitrogen Implanted Silicon Substrates,”0 IEDM Tech. Dig. p. 643, 1997.
Tseng et al., “Thin CVD Stacked Gate Dielectric for ULSI Technology,” IEDM Tech. Dig. p. 321, 1993.
Eimori et al., “ULSI DRAM with Stacked Capacitor Cells for Low Voltage Operation,” IEDM Tech. Dig. p. 45, 1993.
de Muizon Emmanuel
Lutze Jeffrey
Philips Semiconductor Inc.
Wojciechowicz Edward
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