Method of forming dual gate dielectric layer

Details Method of forming dual gate dielectric layer Method of forming dual gate dielectric layer

2006-12-27

2008-10-21

Le, Dung A. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

C257S508000, C257S506000, C257SE21548, C438S259000, C438S427000, C438S426000, C438S424000

Reexamination Certificate

active

07439604

ABSTRACT:
A semiconductor device includes a dual gate dielectric layer that increases a performance of a semiconductor device. The semiconductor device includes a first dielectric layer having a predetermined thickness on a semiconductor substrate. The first dielectric layer is formed on a first region. The semiconductor device also includes a second dielectric layer having a dielectric constant higher than that of the first dielectric layer. The second dielectric layer is formed on both the first region and a second region.

REFERENCES:
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patent: 6271143 (2001-08-01), Mendicino
patent: 6369421 (2002-04-01), Xiang et al.
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patent: 6706577 (2004-03-01), Twu et al.
patent: 6888205 (2005-05-01), Moscatelli et al.
patent: 2003/0003639 (2003-01-01), Kanda et al.

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